Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-09-08
2003-02-25
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S626000, C438S634000, C438S648000, C438S656000, C438S680000, C438S685000, C438S686000, C438S688000, C438S694000, C438S699000
Reexamination Certificate
active
06524946
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of fabricating a semiconductor device having a contact hole, particularly to a method of forming a via hole best suited to a multilayer interconnection structure.
2. Description of the Related Art
There is a multilayer interconnection technique as a technique capable of increasing degree of integration of a semiconductor device. According to the multilayer interconnection technique, an insulating film is formed on a wiring portion on the semiconductor substrate. If the surface of this insulating film is made flat, an etching mask for providing a via hole is formed on the flattened insulating film by a photolithographic process. A selective etching treatment is applied to the insulating film through the etching mask so as to provide a contact hole which reaches the top of the wiring portion positioned under the insulating film. A plug wiring portion is formed in this contact hole, namely, via hole so as to be filled with a conductive material. After the plug wiring portion to be embedded in the via hole is formed, an upper layer interconnection portion connected to the wiring portion serving as a lower wiring portion under the insulating film through the plug wiring portion is formed on the insulating film, thereby realizing a multilayer interconnection structure.
Meanwhile, it is preferable that the diameter of the via hole is set to be large in a manner that the diameter of the plug wiring portion to be connected to the wiring portion under the insulating film substantially conforms to the width dimension or measurement of the wiring portion so as to reduce a wiring resistance.
However, if the opening diameter of the contact hole serving as the via hole is merely increased to conform to the width dimension of the wiring portion, there is a fear of arising a problem that the contact hole or via hole does not accurately reach the top of the lower layer interconnection portion even if there occurs a slight deviation of the location of the etching mask for providing the contact hole from a given position in the photolithographic process, so that the contact hole is open to the other circuit parts at the side of the lower layer interconnection portion.
If the plug wiring portion is formed in the via hole which is deviated from a given position, the plug wiring portion formed in the via hole reaches other circuit parts at the side of the lower wiring portion, entailing an accidental trouble such as a short circuit in the circuits, or unwanted increase of capacitance.
Accordingly, it has been desired so far a method of fabricating a via hole to reduce a wiring resistance without bringing about accidental trouble owing to a tolerance in a photolithographic process.
SUMMARY OF THE INVENTION
To solve the foregoing problems, the invention has the following structure.
A method of fabricating a semiconductor device comprising a semiconductor substrate, an insulating film provided on the semiconductor substrate for embedding therein conductive portions each having a convex configuration, and a contact hole provided in the insulating film and reaching the conductive portions, said method is characterized in further comprising the steps of forming the insulating film for embedding the conductive portions therein so as to represent a convex configuration corresponding to each top of the convex conductive portions, forming an etching stopper film along a surface configuration of the insulating film for covering the insulating film thereby, an etching rate of the etching stopper film being smaller than that of the insulating film, partially removing convex portions of the etching stopper film corresponding to each top of the convex conductive portions, and forming a contact hole by an etching treatment, said contact hole reaching each tops of the convex conductive portions through the removal portion of the etching stopper film.
According to the invention, since the etching stopper film formed under an etching mask is formed on the insulating film along a surface configuration of the insulating film which rises in the portion corresponding to the top of the convex conductive portion to which a contact hole serving as a via hole is open, for example, if the surface of the etching stopper film is removed along the flat surface, only the portion corresponding to each top of the convex conductive portion can be partly removed comparatively precisely.
Accordingly, even if the etching mask is formed at the portion deviated from, for example, a given position, in the selective etching treatment using this etching mask, the etching stopper film to which only the portion corresponding to each top of the convex conductive portions is open comparatively precisely serves as an auxiliary mask operation, thereby preventing the contact hole from being open to the portion deviated from the convex conductive portions.
The insulating film for embedding the convex conductive portions therein can be formed of an silicon oxide film, and the silicon oxide film is formed by a plasma tetraethoxysilane (TEOS) process so that the insulating film having a convex portion corresponding to each top of the convex conductive portions can be suitably formed.
The silicon oxide film for embedding the convex conductive portion therein can be formed by a bias chemical vapor deposition (CVD) process instead of the plasma TEOS process. It is possible to suitably form the insulating film having the convex portion corresponding to the fine convex conductive portion by the employment of the bias CVD process.
As the etching treatment of the insulating film formed of the silicon oxide film, a dry etching including a reaction gas such as fluorine can be employed wherein a silicon nitride film representing the etching rate which is smaller than the silicon oxide film relative to the etching gas can be used as the etching stopper film.
An etchant such as an etching gas or an etching liquid and a material of the etching stopper film can be appropriately selected depending on the kind and characteristic of the insulting film.
It is preferable that the partial removal of the etching stopper film is effected by chemical mechanical polishing (hereinafter referred to as CMP).
Further, the invention is suitable for fabricating a multilayer interconnection structure wherein an interlayer insulating film between the upper layer interconnection portion and a lower layer interconnection portion forms an insulating film.
REFERENCES:
patent: 4944884 (1990-07-01), Beyer et al.
patent: 5246884 (1993-09-01), Jaso et al.
patent: 5387539 (1995-02-01), Yang et al.
patent: 5532191 (1996-07-01), Nakano et al.
patent: 5885587 (1999-03-01), Yamaha et al.
patent: 5892269 (1999-04-01), Inoue et al.
patent: 5998251 (1999-12-01), Wu et al.
patent: 6046084 (2000-04-01), Wei et al.
patent: 6060385 (2000-05-01), Givens
patent: 6171954 (2001-01-01), Hsu
Berry Renee R.
Oki Electric Industry Co. Ltd.
Volentine & Francos, PLLC
LandOfFree
Method of fabricating a semiconductor device having a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating a semiconductor device having a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a semiconductor device having a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3139028