Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral configuration
Reexamination Certificate
2001-01-31
2003-12-16
Park, Ilwoo (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral configuration
C710S003000, C710S008000, C710S009000, C710S104000, C713S001000, C713S100000
Reexamination Certificate
active
06665742
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the initialization of a computing system including a plurality of interconnected devices. More particularly, the present invention relates to initializing a computing system having a bi-directional communication link comprising a plurality of independent sets of unidirectional point-to-point links interconnecting the plurality of devices, the initialization establishing an integrated communication fabric.
2. Background of the Related Art
This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Many computer systems have been designed around a shared bus architecture that generally includes a processing subsystem having one or more processing devices and a system memory connected to a shared bus. Transactions between processing devices and accesses to memory occur on the shared bus, and all devices connected to the bus are aware of any transaction occurring on the bus. In addition to a processing subsystem, many computer systems typically include an input/output (I/O) subsystem coupled to the shared bus via an I/O bridge that manages information transfer between the I/O subsystem and the processing subsystem. Many I/O subsystems also generally follow a shared bus architecture, in which a plurality of I/O or peripheral devices are coupled to a shared I/O bus. The I/O subsystem may include several branches of shared I/O buses interconnected via additional I/O bridges.
Such shared bus architectures have several advantages. For example, because the bus is shared, each of the devices coupled to the shared bus is aware of all transactions occurring on the bus. Thus, transaction ordering and memory coherency is easily managed. Further, arbitration among devices requesting access to the shared bus can be simply managed by a central arbiter coupled to the bus. For example, the central arbiter may implement an allocation algorithm to ensure that each device is fairly allocated bus bandwidth according to a predetermined priority scheme.
Shared buses, however, also have several disadvantages. For example, the multiple attach points of the devices coupled to the shared bus produce signal reflections at high signal frequencies which reduce signal integrity. As a result, signal frequencies on the bus are generally kept relatively low to maintain signal integrity at an acceptable level. The relatively low signal frequencies reduce signal bandwidth, limiting the performance of devices attached to the bus. Further, the multiple devices attached to the shared bus present a relatively large electrical capacitance to devices driving signals on the bus, thus limiting the speed of the bus. The speed of the bus also is limited by the length of the bus, the amount of branching on the bus, and the need to allow turnaround cycles on the bus. Accordingly, attaining very high bus speeds (e.g., 500 MHz and higher) is difficult in more complex shared bus systems.
The problems associated with the speed performance of a shared bus system may be addressed by implementing the bus as a bi-directional communication link comprising a plurality of independent sets of unidirectional point-to-point links. Each set of unidirectional links interconnects two devices, and each device may implement one or more sets of point-to-point links. Thus, multiple devices can be connected in a variety of configurations, such as a daisy chain, a ring, a ring connected to a daisy chain, interconnected daisy chains, interconnected rings, etc.
In systems having a communication link implemented as a plurality of independent sets of point-to-point links, initialization of the system to yield an integrated “fabric” of interconnected devices that can communicate with each other can be more complex than the initialization of a system in which devices communicate on a shared bus. For example, in shared bus systems, the devices generally all communicate at the same frequency using the same transmitter/receiver widths. The common frequency and widths may be determined by examining the shared bus. Further, because all of the devices are connected to the shared bus, the locations of all of the devices are known and can be reached during the initialization procedure.
In a point-to-point link system, however, the system's devices are not connected to a common bus, and thus cannot determine common communication parameters (e.g., clock frequency, transmitter and receiver widths, etc.) simply by looking at a single bus. Indeed, devices in point-to-point link systems are unaware of the parameters and the locations of other devices which are not directly connected to that particular device. Thus, it would be desirable to provide an initialization scheme for point-to-point link systems that includes a low-level initialization of each link that enables the devices at the ends of each link to communicate in a compatible manner. Then, initialization at a system level to establish an integrated fabric may proceed, including definition of routing directions and optimization of transmitter and receiver frequencies and widths.
Because point-to-point link systems may be configured in a variety of structures, it would be desirable to provide an initialization scheme at the system level that results in the determination and definition of the physical and logical structure of the computing system, including the identification of the location of each device in the system. For example, in point-to-point link systems having a ring structure, a communication between two devices may take several different routes through a variety of other devices before reaching its destination. Thus, such a system initialization procedure would establish the location of each device relative to the other device, provide each device with a unique identifier, and optimize routing paths for communications among the devices. The routing paths may then be placed in routing tables or maps for each device.
In point-to-point link systems having a daisy-chain structure, the devices in the chain often are subservient to a master device, such as a bridge device, connected to one end of the chain. In such systems, communication protocols may dictate that communications should be routed in a particular direction, such as towards the master device. Thus, it would be desirable to provide an initialization scheme for a system having a daisy-chain structure that provides each device with a unique identifier and determines the direction in which the master device is located such that communications may be routed in an appropriate manner.
In addition to routing, daisy-chain structures introduce other complexities that should be addressed by the initialization process. For example, because the devices in the chain are unaware of transactions occurring between other devices in the chain, a device sending a communication down the chain may not be aware of acceptance of the communication by another device. Accordingly, it would be desirable to provide an initialization scheme that results in the definition of the physical and/or logical end of the chain, such that an error message may be generated by the device at the end of the chain if a communication is not accepted by any device on the chain.
Still further, even though the low-level initialization of the links establishes default compatible communication frequencies and widths, communications among device may occur more efficiently by allowing the transmitters and receivers of the devices at the ends of each point-to-point link to communicate using the maximum compatible communication frequencies and width for the respective transmi
Hummel Mark D.
Meyer Derrick R.
Owen Jonathan M.
Advanced Micro Devices , Inc.
Kivlin B. Noäl
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Park Ilwoo
LandOfFree
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