Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-08-07
2003-12-09
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S291000, C257S461000
Reexamination Certificate
active
06661047
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to improved semiconductor imaging devices and, in particular, to CMOS imagers with improved color separation and sensitivity.
BACKGROUND OF THE INVENTION
The semiconductor industry currently uses different types of semiconductor-based imagers, such as charge coupled devices (CCDs), photodiode arrays, charge injection devices and hybrid focal plane arrays, among others.
CCD technology is often used for image acquisition and has a number of advantages which makes it the preferred technology, particularly for small size imaging applications. CCDs are capable of large formats with small pixel size and they employ low noise charge domain processing techniques. CCD imagers suffer, however, from a number of disadvantages. For example, they are susceptible to radiation damage, they exhibit destructive read-out over time, they require good light shielding to avoid image smear and they have a high power dissipation for large arrays. In addition, while offering high performance, CCD arrays are difficult to integrate with CMOS processing in part due to a different processing technology and to their high capacitances, complicating the integration of on-chip drive and signal processing electronics with the CCD array. Further, CCDs may suffer from incomplete charge transfer from pixel to pixel which results in image smear.
Because of the inherent limitations in CCD technology, CMOS imagers have been increasingly used as low cost imaging devices. A filly compatible CMOS sensor technology enabling a higher level of integration of an image array with associated processing circuits would be beneficial to many digital applications such as, for example, in cameras, scanners, machine vision systems, vehicle navigation systems, video telephones, computer input devices, surveillance systems, auto focus systems, star trackers, motion detection systems, image stabilization systems and data compression systems for high-definition television.
CMOS imagers have several advantages over CCD imagers, such as, for example, low voltage operation and low power consumption, compatibility with integrated on-chip electronics (control logic and timing, image processing, and signal conditioning such as A/D conversion), random access to the image data, and lower fabrication costs. Additionally, low power consumption is achieved for CMOS imagers because only one row of pixels at a time needs to be active during the readout and there is no charge transfer (and associated switching) from pixel to pixel during image acquisition. On-chip integration of electronics is particularly advantageous because of the potential to perform many signal conditioning functions in the digital domain (versus analog signal processing) as well as to achieve a reduction in system size and cost.
A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including either a photogate, photoconductor or a photodiode overlying a doped region of a substrate for accumulating photo-generated charge in the underlying portion of the substrate. A readout circuit is connected to each pixel cell and includes at least an output field effect transistor formed in the substrate and a charge transfer section formed on the substrate adjacent the photogate, photoconductor or photodiode having a sensing node, typically a floating diffusion node, connected to the gate of an output transistor. The imager may include at least one electronic device such as a transistor for transferring charge from the charge accumulation region of the substrate to the floating diffusion node and one device, also typically a transistor, for resetting the node to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to the floating diffusion node accompanied by charge amplification; (4) resetting the floating diffusion node to a known state before the transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the floating diffusion node. The charge at the floating diffusion node is typically converted to a pixel output voltage by a source follower output transistor. The photosensitive element of a CMOS imager pixel is typically either a depleted p-n junction photodiode or a field induced depletion region beneath a photogate. For photodiodes, image lag can be eliminated by completely depleting the photodiode upon readout.
A schematic view of an exemplary CMOS imaging circuit is illustrated in FIG.
1
. As it will be described below, the CMOS imaging circuit includes a photogate for accumulating photo-generated charge in an underlying portion of the substrate. It should be understood, however, that the CMOS imager may include a photodiode or other image to charge converting device, in lieu of a photogate, as the initial accumulator for photo-generated charge.
FIG. 1
shows a simplified photodetector circuit for a pixel cell
14
of an exemplary CMOS imager using a photogate and a readout circuit
60
. It should be understood that while
FIG. 1
shows the circuitry for operation of a single pixel, in practical use there will be an M x N array of pixels arranged in rows and columns with the pixels of the array accessed using row and column select circuitry, as described in more detail below.
The pixel cell
14
is shown in part as a cross-sectional view of a semiconductor substrate
16
, which is typically a p-type silicon, having a surface well of p-type material
20
. An optional layer
18
of p-type material may be used, if desired. Substrate
16
may be formed of Si, SiGe, Ge, or GaAs, among others. Typically, the entire semiconductor substrate
16
is a p-type doped silicon substrate including a surface p-well
20
(with layer
18
omitted), but many other options are possible, such as, for example p on p− substrates, p on p+ substrates, p-wells in n-type substrates or the like.
An insulating layer
22
of silicon dioxide, for example, is formed on the upper surface of p-well
20
. The p-type layer may be a p-well formed in substrate
16
. A photogate
24
, thin enough to pass radiant energy or of a material which passes radiant energy, is formed on the insulating layer
22
. The photogate
24
receives an applied control signal PG which causes the initial accumulation of pixel charges in n+ region
26
. An n+ type region
26
, adjacent to one side of the photogate
24
, is formed in the upper surface of p-well
20
. A transfer gate
28
is formed on insulating layer
22
between the n+type region
26
and a second n+ type region
30
formed in p-well
20
. The n+ regions
26
and
30
and transfer gate
28
form a charge transfer transistor
29
which is controlled by a transfer signal TX. The n+ region
30
is typically called a floating diffusion region. The n+ region
30
is also a node for passing charge accumulated thereat to the gate of a source follower transistor
36
described below.
A reset gate
32
is also formed on insulating layer
22
adjacent and between the n+ type region
30
and another n+ region
34
which is also formed in p-well
20
. The reset gate
32
and n+ regions
30
and
34
form a reset transistor
31
which is controlled by a reset signal RST. The n+ type region
34
is coupled to voltage source V
DD
, of for example, 5 volts. The transfer and reset transistors
29
,
31
are n-channel transistors as described in this implementation of a CMOS imager circuit in a p-well. As known in the art, it is also possible to implement a CMOS imager in an n-well, in which case each of the transistors would be p-channel transistors. It should also be noted that, while
FIG. 1
shows the use of a transfer gate
28
and associated transistor
29
, this structure provides ad
Dickstein , Shapiro, Morin & Oshinsky, LLP
Micro)n Technology, Inc.
Ngo Ngan V.
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