Semiconductor memory device having redundant circuit

Details Semiconductor memory device having redundant circuit Semiconductor memory device having redundant circuit

1991-08-22

1993-12-21

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Bad bit

365210, 365233, G11C 1300

Patent

active

052726720

ABSTRACT:
An output of a column redundant circuit is supplied to one spare column selection line. The spare column selection line is provided to select the spare column line. The column redundant circuit includes four spare column decoders of the same number as that of the memory cell arrays which can be selected by the column selection line supplied with an output of a partial column decoder, and an OR gate for deriving the logical sum of outputs of the four spare column decoders and supplying the same to the spare column selection line. An output of the OR gate is supplied to a logic circuit together with an output of the partial column decoder.

REFERENCES:
patent: 4951253 (1990-08-01), Sahara et al.
patent: 5025418 (1991-06-01), Asoh
patent: 5033024 (1991-07-01), O'Connell
"A Divided Word-Line Structure in the Static RAM and Its Application to a 64K Full CMOS RAM", IEEE Journal of Solid-State Circuits, vol. SC-18, No. 5, Oct. 1983, pp. 479-485.
"A 256K Dynamic RAM with Page-Nibble Mode", IEEE Journal of Solid-State Circuits, vol. SC-18, No. 5, Oct. 1983, pp. 470-478.

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