Semiconductor memory device with redundancy structure and proces

Details Semiconductor memory device with redundancy structure and proces Semiconductor memory device with redundancy structure and proces

1991-04-02

1993-12-21

Mottola, Steven

Static information storage and retrieval

Read/write circuit

Bad bit

365178, G11C 700, G11C 1134

Patent

active

052726711

ABSTRACT:
A nonvolatile semiconductor memory device comprises a memory cell array and a redundant circuit. The memory cell array comprises a plurality of cell lines for storing fixed data. The redundant circuit comprises redundancy memory cell rows of MOS transistors, and at least one redundancy spare decoder by which at least one of the redundancy memory cell rows is selectively determined and permuted with a memory cell to be repaired. At least one of the redundancy memory cell rows has data to be recovered stored therein. The data to be recovered is stored in the redundancy memory cell rows by selectively implanting channel regions of the memory cell rows with an impurity ion of high energy.

REFERENCES:
patent: 4393474 (1983-07-01), McElroy
IEEE/IRPS '90 186-192 (Oxide-Nitride-Oxide Antifuse Reliability) Jul. 1990.

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