Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
Reexamination Certificate
2000-11-02
2003-12-02
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Data formatting to improve error detection correction...
C714S755000, C714S784000
Reexamination Certificate
active
06658605
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multiple coding method and apparatus and a multiple decoding method and apparatus for detecting and correcting (or checking) errors that have occurred in a transmission medium, such as an optical cable, disposed in an information transmission system, or a storage medium, such as a hard disk drive, disposed in an information processing system. It also relates to an information transmission system including such a multiple coding apparatus and such a multiple decoding apparatus. More particularly, the present invention relates to an improvement in a multiple coding and decoding arrangement, typified by a product coding and decoding arrangement or a concatenated coding and decoding arrangement, aimed for improving error detecting and correcting performances, which is employed to efficiently reduce a delay in the information transmission caused by the multiple coding and decoding technique, thus providing a high transmission rate.
2. Description of the Prior Art
Prior art techniques of performing coding a number of times are disclosed by H. Imai, “Coding theory”, published in 1990 by the Institute of Electronics, Information and Communication Engineers, Japan, and Japanese patent application publication (TOKKAIHEI) No. 10-190486, for example. Referring now to
FIG. 6
, there is illustrated a block diagram showing the structure of a prior art information transmission system for performing coding and decoding a number of times and for transmitting a sequence of pieces of information. In the figure, reference numeral
29
denotes a concatenated coding apparatus, numeral
30
denotes a concatenated decoding apparatus, and numeral
3
denotes a transmission medium connected between the concatenated coding apparatus
29
and the concatenated decoding apparatus
30
.
The concatenated coding apparatus
29
includes an information sequence input circuit
31
for receiving an input sequence of pieces of information, a Reed-Solomon outer encoder
32
for encoding the input information sequence, an interleaving memory
33
for sequentially storing a plurality of outer coded sequences from the Reed-Solomon outer encoder, an address generating circuit
34
for controlling writing and reading to and from the interleaving memory
33
, an Reed-Solomon inner encoder
35
for further encoding an input sequence read out of the interleaving memory
33
, and a concatenated coded sequence output circuit
36
for furnishing a sequence of inner coded data from the Reed-Solomon inner encoder as an output sequence of concatenated coded data to the transmission medium
3
.
The concatenated decoding apparatus
30
includes a concatenated coded sequence input circuit
37
for receiving an input sequence of concatenated coded data, an Reed-Solomon inner decoder
38
for decoding the input concatenated coded sequence, a de-interleaving memory
39
for sequentially storing a plurality of sequences of inner decoded data from the Reed-Solomon inner decoder, an address generating circuit
40
for controlling writing and reading to and from the de-interleaving memory
39
, an Reed-Solomon outer decoder
41
for further decoding a sequence of decoded data read out of the de-interleaving memory, and an information sequence output circuit
42
for furnishing a sequence of outer decoded data from the Reed-Solomon outer decoder as an output sequence of pieces of information.
In operation, when an information sequence is applied to the information sequence input circuit
31
, the Reed-Solomon outer encoder
32
encodes the input information sequence and sequentially stores the outer coded sequence from the outer encoder in the interleaving memory
33
. When a predetermined number of outer coded sequences are written into the interleaving memory
33
, the address generating circuit
34
makes the interleaving memory
33
sequentially furnish those sequences in an order opposite to the order in which they have been written into the interleaving memory. The Reed-Solomon inner encoder
35
further encodes the plurality of data sequences read out of the interleaving memory and generates a plurality of inner coded sequences, and the concatenated coded sequence output circuit
36
then furnishes the plurality of inner coded sequences from the Reed-Solomon encoder as a plurality of concatenated coded sequences to the transmission medium
3
.
When the concatenated coded sequence input circuit
37
receives an input concatenated coded sequence of by way of the transmission medium
3
, the Reed-Solomon inner decoder
38
decodes the input concatenated coded sequence and then stores the decoded result in the de-interleaving memory
39
sequentially. When a predetermined number of sequences of inner decoded data are written into the de-interleaving memory, the address generating circuit
40
makes the de-interleaving memory
39
sequentially furnish those sequences in an order opposite to the order in which they have been written into the de-interleaving memory. The Reed-Solomon outer decoder
41
further decodes the plurality of data sequences read out of the de-interleaving memory and generates a plurality of sequence of outer decoded data, and the information sequence output circuit
42
then furnishes the plurality of sequence of outer decoded data as a plurality of sequences of output information sequentially.
In this way, the prior art information transmission system can sequentially supply a plurality of information sequences to the concatenated coding apparatus
29
, and then transmit a plurality of concatenated coded sequences generated by the concatenated coding apparatus
29
, by way of the transmission medium
3
, to the concatenated decoding apparatus
30
which decodes the plurality of concatenated coded sequences, so that the receive side of the system can get the plurality of information sequences error-detected and error-corrected.
A problem with prior art information transmission systems constructed as above is that in the concatenated coding apparatus
29
, for example, the interleaving memory
33
has to have enough storage amount to sequentially store a predetermined number of outer coded sequences generated by the Reed-Solomon outer encoder
32
because the plurality of outer coded sequences must be sequentially read out of the interleaving memory
33
in an order opposite to the order in which they have been written into the interleaving memory in order to make the coding directions of the two encoders
32
and
35
differ from each other, thereby providing high error-detecting and error-correcting performances, and it is therefore impossible to read the next set of outer coded sequences until the writing of the previous set of outer coded sequences to the interleaving memory
33
is completed, thus causing a very long time delay in the coding process.
Referring next to
FIG. 7
, there is illustrated a format diagram for explaining the writing and reading operations of the interleaving memory
33
of the prior art information transmission system of FIG.
6
.
FIG. 7
shows an example in which the plurality of outer coded sequences from the Reed-Solomon outer encoder are written into the interleaving memory
33
such that they are running along columns from the leftmost column to the rightmost column, and a plurality of rows are sequentially read out of the interleaving memory, starting from the uppermost row, after the last outer coded sequence is written into the rightmost column. In the case of the use of such the interleaving memory
33
, the reading process of reading the plurality of coded sequences running along rows cannot be performed until the writing process of writing the plurality of outer coded sequences into the memory locations from the leftmost column to the rightmost column is completed, thus causing a time delay.
FIG. 8
shows an example in which the plurality of outer coded sequences are written into the interleaving memory
33
such that each of them is split across some columns.
Consequently, the total
Fujita Hachiro
Kubo Kazuo
Miyata Yoshikuni
Nakamura Takahiko
Yoshida Hideo
Chung Phung M.
Mitsubishi Denki & Kabushiki Kaisha
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