Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2000-09-29
2003-10-14
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
With measuring or testing
C438S003000, C438S149000
Reexamination Certificate
active
06632686
ABSTRACT:
FIELD
The present invention generally relates to the fabrication and design of devices and integrated circuits. More particularly, the present invention relates to the fabrication and design of silicon on insulator (SOI) devices.
BACKGROUND
The traditional integrated circuits fabrication process is a series of steps by which a geometric pattern or set of geometric patterns is transformed into an operating integrated circuit. An integrated circuit (IC), may include superimposed layers of conducting, insulating, and transistor-forming materials, usually formed on a silicon wafer substrate. By arranging, constructing and fabricating predetermined geometric shapes in each of these superimposed layers, an integrated circuit that performs the desired function may be constructed. The overall fabrication process typically includes of the patterning of a particular sequence of successive layers using lithography to define them and etch by various chemicals to remove portions of the various layers. Many different processes exist for creating a pattern on the underlying silicon wafer with different processes being specifically adapted to produce the desired type of integrated circuit.
Processes have been developed for fabricating integrated circuit devices commonly known as silicon on insulator (SOI) devices. SOI devices are semiconductor devices fabricated within a relatively thin silicon layer that overlies an electrically insulating region formed over a substrate material. This insulating region may include, for example, a layer of SiO
2
deposited or grown over a semiconductor substrate material such as silicon or gallium arsenide. The SOI fabrication process allows circuit devices to be created that are electrically isolated from the underlying substrate.
SOI devices offer several advantages over more conventional semiconductor devices. For example, SOI devices may have lower power consumption requirements than other types of devices that perform similar tasks. SOI devices may also have lower parasitic capacitances than non-SOI devices. This translates into faster switching times for the resulting circuits. In addition, the phenomenon of “latchup,” which is often exhibited by complementary metal-oxide semiconductor (CMOS) devices, may be avoided when circuit devices are manufactured using SOI fabrication processes. SOI devices are also less susceptible to the adverse effects of ionizing radiation and, therefore, tend to be more reliable in applications where ionizing radiation may cause operation errors.
SOI has been proposed for high performance CMOS ICs with a floating body node. Keeping the body of the SOI floating may provide a better circuit delay and since no body contact is necessary, then better front-end transistor dominated circuit density may be achieved. A floating body node causes the floating body effect (FBE), which makes circuit design challenging. One example of floating body effect is the history effect that a designer needs to margin (guard band) for when designing integrated circuits. History effect means that the circuit delay is a function of the previous status of the circuit as determined by switching of the gate and drain transistor signals. Floating body effect modulates the device threshold voltage in static CMOS circuits, for example, such that a threshold voltage change causes the device drive current to vary, which in turn causes changes in circuit delay. History effect refers to this variability in delay and is determined based on input history and conditions prior to switching activity. The history effect of the delay in SOI is a design obstacle for adopting SOI technology.
REFERENCES:
patent: 4785202 (1988-11-01), Toyoda
patent: 5202841 (1993-04-01), Tani
patent: 5345401 (1994-09-01), Tani
patent: 5416859 (1995-05-01), Burns et al.
patent: 5579005 (1996-11-01), Moroni
patent: 5661579 (1997-08-01), Takahashi
patent: 5767549 (1998-06-01), Chen et al.
patent: 5780341 (1998-07-01), Ogura
patent: 5818407 (1998-10-01), Hori et al.
patent: 5862086 (1999-01-01), Makimura et al.
patent: 5909264 (1999-06-01), Fujikawa et al.
patent: 5933062 (1999-08-01), Kommrusch
patent: 5956597 (1999-09-01), Furukawa et al.
patent: 5995398 (1999-11-01), Yamauchi et al.
patent: 6020222 (2000-02-01), Wollesen
patent: 6043166 (2000-03-01), Roitman et al.
patent: 6058041 (2000-05-01), Golke et al.
patent: 6085041 (2000-07-01), Shiokama
patent: 6090689 (2000-07-01), Sadana et al.
patent: 6110765 (2000-08-01), Manning
patent: 6118505 (2000-09-01), Nagata et al.
patent: 6121812 (2000-09-01), Tsukikawa
patent: 6140672 (2000-10-01), Arita et al.
patent: 6229170 (2001-05-01), Sakao
patent: 6262907 (2001-07-01), Lien et al.
patent: 6292907 (2001-09-01), Miller
patent: 6321365 (2001-11-01), McBride
De Vivek K.
Keshavarzi Ali
Narendra Siva G.
Tschanz James W.
Antonelli Terry Stout & Kraus LLP
Jr. Carl Whitehead
Schillinger Laura M
LandOfFree
Silicon on insulator device design having improved floating... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Silicon on insulator device design having improved floating..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Silicon on insulator device design having improved floating... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3136755