Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-01-09
2003-11-25
Zarabian, Amir (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S675000, C438S751000
Reexamination Certificate
active
06653226
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to surface planarization technology. More specifically, it relates to electroplanarization technology for planarizing surfaces having low aspect ratio recesses or trenches. Even more specifically, the invention pertains to electrochemical planarization of copper or other metals deposited on partially fabricated integrated circuits.
BACKGROUND OF THE INVENTION
In the fabrication of integrated circuits, as the number of levels in an interconnect technology is increased, the stacking of additional layers on top of one another produces a more and more rugged topography. Without planarization, the microscopic canyons that result on the integrated circuit surface from stacking of device features create a topography that would eventually lead to defects in the integrated circuit that would make the circuit unusable.
One method of planarization used in the art is chemical mechanical polishing (CMP). CMP is a process that uses a mixture of abrasives and pads to polish the surface of the integrated circuit. Unfortunately, CMP polishing techniques are difficult to control; the end-point can be difficult to detect. They are also expensive. The high equipment and waste handling cost and low throughput contribute the overall expense of CMP.
Another method of planarization involves an electrolytic technique known as electropolishing. Electropolishing is a low cost alternative technique to CMP. Lower capital cost, easier waste handling, and much higher processing rates make it a desirable alternative to CMP. Electropolishing is a method of polishing metal surfaces by applying an electric current through an electrolytic bath, as described for example in McGraw-Hill Encyclopedia of Science & Technology, pp. 810-811, 1982. The process may be viewed as the reverse of electroplating.
Various US patents describe such electropolishing during IC fabrication. Examples include U.S. Pat. No. 5,096,550 to Mayer et al. ('550 patent), U.S. Pat. No. 3,849,270 to Takagi et al., and U.S. Pat. No. 5,256,565 to Bernhardt et al. Each of these patents is incorporated herein by reference for all purposes.
A problem arises during the electropolishing of surfaces in which low aspect ratio features exist. For example, refer to FIG.
1
A and FIG.
1
B.
FIG. 1A
depicts a cross-sectional layer of a partially fabricated integrated circuit
101
in which trenches have been cut in dielectric layer
103
(for a damascene process), and subsequently filled and covered with deposited metal
105
. Once deposited metal
105
is electropolished to the dielectric surface, the metal remaining in the trenches will define conductive lines and contact pads for the integrated circuit. High aspect ratio (larger depth than width) features are characterized by trenches with small widths,
107
. These are typically used for conductive lines and vias. Low aspect ratio (larger width than depth) features are characterized by trenches with large widths,
109
. These are typically used for contact pads. Today, features that vary in size by two orders of magnitude are typical. A 1 &mgr;m deep feature can have widths of from 0.2 &mgr;m to 100 &mgr;m.
Typically, conformal metalization processes are used to conformally deposit metal
105
onto dielectric
103
. Because electroplating is highly isotropic, it can be shown both theoretically and experimentally that high aspect ratio features (i.e. depth to width >3:1) are rapidly filled. Therefore, electroplating is a preferred method of metalization. Typically a metalization thickness of ½ the feature width is needed to close the cleft over high aspect ratio features. Further addition of metal, needed to fill low aspect ratio features, not only closes the cleft over high aspect ratio features, but forms protruding regions
111
, relative to field regions
113
. When enough metal is deposited to completely fill low aspect ratio features, the fill profile over these features exhibit large recesses
115
, nearly equal to the original feature depth. Electroplating is not typically continued to “close” recesses
115
because to do so would require depositing a very thick metal layer, which would be uneconomical to add and later remove using conventional CMP or electropolishing technology.
Conventional electropolishing techniques can planarize a surface in which the feature to be planarized is no more than perhaps three times as wide as it is deep. For features wider than these, the rate of removal is essentially uniform everywhere.
FIG. 1B
depicts a cross-sectional layer of partially fabricated integrated circuit
101
after conventional electropolishing. As seen in
FIG. 1B
, although protruding regions
111
and field regions
113
of metal
105
are electropolished effectively to the dielectric surface level over the high aspect ratio features; recesses
115
are propagated and expanded to produce recesses
117
. Recesses
117
span the width of low aspect ratio features leaving effectively no metal in the pad regions. Obviously, this is an unacceptable result.
The current state of electropolishing technology has additional difficulties. For example, electropolishing typically requires highly viscous electrolyte baths (e.g., 85% phosphoric acid (H
3
PO
4
) in water, or with some added ethylene glycol). While these baths are effective in achieving good polishing and planarization rates, they make it difficult to remove defect-causing bubbles and to handle the fluids in general. Note that a hydrogen generating reaction may take place at the cathode. The hydrogen can become entrained in the electrolyte, complicating tool design and presenting a potential safety hazard. In addition, these baths also have high resistivities, making for large power requirements and substantial amounts of generated heat (which must be removed to maintain a constant process control).
What is needed therefore is improved technology for planarizing conductive layers on integrated circuits and other substrates.
SUMMARY OF THE INVENTION
The present invention provides methods and apparatus for electrochemical planarization of an electrically conductive material surface with varying topography from a partially fabricated integrated circuit, in which protruding regions of the conductive material are removed more quickly than recessed regions to thereby increase the planarity of the conductive material surface.
The invention accomplishes this by providing a cell in which variations in the topology of a wafer surface correspond to significant variations in the resistance of electrolyte in the cell. Regions with protruding features have low electrolyte resistance. Regions with recessed features have significantly higher resistance. Hence regions with protruding features are polished significantly faster than regions with recessed features. As the topological variations decrease during electroplanarization, the variations in resistance (and hence planarization rate) also decrease. Cells and methods of this invention attain the significant variations in resistance by maintaining very small separations between the anode (wafer) and the cathode, and by using a highly resistive electrolyte.
Another aspect of this invention pertains to methods of electrochemical planarization of metals such as copper from partially fabricated integrated circuits. These methods may be characterized by the following elements: (a) using the partially fabricated integrated circuit as an anode in an electrochemical cell; (b) positioning the anode's and a cathode's active surfaces in very close proximity, such that their active surfaces are separated only by the electrolyte medium and its constituents; (c) using an essentially continuous flow of highly resistive electrolyte over the active surfaces of the anode and cathode; (d) moving the anode and cathode progressively closer during electrochemical planarization; and (e) controlling the distance between the anode and the cathode within sub-micron scale distances during electrochemical planarization. From herein, the term wafer is meant to
Beyer Weaver & Thomas LLP
Novellus Systems Inc.
Perkins Pamela E
Zarabian Amir
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