Semiconductor device with lightly doped drain layer

Details Semiconductor device with lightly doped drain layer Semiconductor device with lightly doped drain layer

1999-10-08

2003-06-10

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S336000, C257S344000, C257S350000, C438S301000, C438S302000, C438S305000

Reexamination Certificate

active

06576965

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device for a semiconductor LSI, and more particularly to a lightly doped drain (hereinafter, referred to as LDD) layer structure and a technique of forming the same.
2. Description of the Background Art
An LDD layer structure has been conventionally used in a MOSFET to prevent deterioration in hot carrier. For example,
FIG. 10
is a vertical section showing an n-type MOSFET with single LDD layer structure as a first prior art. As shown in
FIG. 10
, a semiconductor device
1
P
1
where a gate insulating film
11
P and a gate electrode
5
P are formed in this order on a surface of a semiconductor substrate
2
P having a p-well formed by ion-implantation with boron (B) is once implanted with phosphorus (P) ion or arsenic (As) ion to form LDD layers
8
P and
10
P almost symmetrically and after that, a sidewall
6
P is formed and then arsenic ion or the like is further implanted and diffused to form high-concentration (n
+
) source/drain regions
3
P and
4
P. For reference, a flow of manufacturing the n-type MOSFET of
FIG. 10
is shown in FIG.
11
.
As a second prior art which is a variation of the first prior art, an n-type MOSFET with double LDD layer structure is proposed in Japanese Patent Application Laid Open Gazette No. 7-297393. The structure of this n-type MOSFET
1
P
2
is shown in FIG.
12
. In the n-type MOSFET
1
P
2
of
FIG. 12
, an arsenic ion is once implanted to form the inner LDD layers
8
P and
10
P in the same manner as the first prior art, and outer LDD layers
7
P and
9
P made of P layer with high diffusion coefficient are formed by utilizing diffusion through a heat treatment, covering the inner LDD layers
8
P and
10
P, respectively.
(1) The MOSFET with single LDD layer structure of the first prior art has an advantage that the LDD layers (arsenic layers
8
P and
10
P of
FIG. 10
) relieve a drain electric field to thereby improve hot-carrier resistance and withstand voltage. On the other hand, the MOSFET with single LDD layer structure has a disadvantage that the LDD layers work as parasitic resistance between the source and drain to thereby deteriorate driving capability.
(2) In the double LDD layer structure of the second prior art, a double-layered structure consisting of the outer P layer of relatively low concentration and the inner arsenic layer of relatively high concentration located near a surface forms a step-like impurity concentration distribution, and therefore the LDD layer made of P of relatively low concentration relieves the drain electric field and the LDD layer made of arsenic of relatively high concentration reduces the resistance element, to thereby achieve a driving capability higher than the first prior art.
This structure of the second prior art, however, causes a new problem that a region where a sum of the concentration distributions of the arsenic layer of relatively high concentration and the phosphorus layer of relatively low concentration varies in a step-like manner is created inside the semiconductor substrate, to locally generate a strong electric field therein, and consequently the hot-carrier resistance is deteriorated as compared with the structure of the first prior art. To clarify this point, an impurity concentration distribution with respect to a horizontal direction in parallel with the surface of the semiconductor substrate (an impurity concentration distribution at the depth of 0.5 &mgr;m inside the semiconductor substrate from an interface between the gate insulating film and the surface of the semiconductor substrate) in the n-type MOSFET of double LDD structure as shown in
FIG. 12
of Japanese Patent Application Laid Open Gazette No. 7-297393 is simulated by the inventor of the present invention. The simulation result (not known) is shown in FIG.
13
.
In
FIG. 13
, the horizontal axis represents a horizontal direction x of
FIG. 12
with the position x=0.001 &mgr;m indicating a center portion of the surface of the semiconductor substrate
2
P sandwiched by end portions of the phosphorus layers
7
P and
9
P (n
−
(2)) of
FIG. 12
, and the vertical axis y of
FIG. 13
represents a vertical direction y from the center portion towards the inside of the semiconductor substrate
2
P. As shown in
FIG. 13
, the concentration of phosphorus which is an impurity element of the outer LDD layer increases from 1E16 cm
−3
to 1E18 cm
3
with relatively great gradient and from the position x=0.08 &mgr;m of
FIG. 13
, the concentration of arsenic sharply increases with a gradient greater than that of phosphorus. Since the inner LDD layers
8
P and
10
P of
FIG. 12
include both impurities, phosphorus and arsenic, the impurity concentration of the inner LDD layers
8
P and
10
P is the sum of both concentrations of phosphorus and arsenic from the position x=0.08 &mgr;m of
FIG. 13
(end portions of the LDD layers
8
P and
10
P) and therefore sharply increases. Especially, at an intersection P
1
of
FIG. 13
, as the concentrations of both impurities, that is, phosphorus and arsenic are equal to each other, the impurity concentration of the LDD layers
8
P and
10
P of
FIG. 12
sharply increases up to almost twice in a step-like manner. Further, since a region P
2
of
FIG. 13
is a junction between the LDD layer
8
P (
10
P) and n
+
layer
3
P (
4
P), the concentration connection becomes a step-like one also in this region.
Thus, it is disadvantageous that the second prior art can show only intermediate characteristics between the single LDD layer structure of the first prior art and a single drain structure in an integrated evaluation of its characteristics such as driving capability, withstand voltage and hot-carrier resistance.
SUMMARY OF THE INVENTION
The present invention is directed to a semiconductor device. According to a first aspect of the present invention, the semiconductor device comprises: a semiconductor substrate having a channel impurity of a first conductivity type; a first high-concentration impurity region formed from a first surface region in a surface of the semiconductor substrate towards the inside of the semiconductor substrate, having at least one kind of impurity of a second conductivity type whose concentration is higher than that of the channel impurity; an insulating film formed on a second surface region adjacent to the first surface region in the surface of the semiconductor substrate; a control electrode formed on a surface of the insulating film; a second high-concentration impurity region formed from a third surface region adjacent to the second surface region in the surface of the semiconductor substrate towards the inside of the semiconductor substrate, being opposed to the first high-concentration impurity region, having the at least one kind of impurity identical to that of the first high-concentration impurity region; and a first lightly doped drain layer formed from a fourth surface region in the second surface region on the side of an interface between the first and second surface regions towards the inside of the semiconductor substrate, being joined to at least part of an end surface of the first high-concentration impurity region opposed to the second high-concentration impurity region, having a first impurity of the second conductivity type whose concentration is lower than that of the at least one kind of impurity in the first and second high-concentration impurity regions. In the semiconductor device of the first aspect, the first lightly doped drain layer comprises a first main distribution having a first concentration gradient corresponding to an impurity concentration variation with respect to a horizontal direction in which an end surface of the control electrode is viewed from a center portion of the control electrode in parallel to the surface of the semiconductor substrate, where the first impurity is distributed inside the semiconductor substrate; and a first tail distribution having a second concentration gradie

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