Semiconductor integrated circuit device with processor

Details Semiconductor integrated circuit device with processor Semiconductor integrated circuit device with processor

1999-10-26

2003-02-18

Iqbal, Nadeem (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S045000

Reexamination Certificate

active

06523136

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device with a processor, and in particular a semiconductor integrated circuit device with a processor allowing easy debugging.
2. Description of the Background Art
Processors such as an MPU (Microprocessor Unit) and a CPU (Central Processor Unit) are subjected to debugging such as verification of programs and verification of hardware operations. For facilitating such debugging, a debug support unit for supporting the debug operation is conventionally arranged within a processor. Particularly in a so-called “system-on-chip” structure with a processor and a peripheral LSI (Large Scale Integrated Circuit Device) integrated on a single chip, complicated internal structures must be operated accurately, and the debugging is required.
FIG. 15
schematically shows internal structures of a semiconductor integrated circuit device with a processor and a debug environment in the prior art. In
FIG. 15
, semiconductor integrated circuit device
1
with a processor (which will be referred to as “LSI with CPU
1
” hereinafter) includes a CPU core
2
for performing a processing instructed by an instruction applied thereto, a Read-Only Memory (ROM)
4
for storing a program, a Random Access Memory (RAM)
5
for retaining intermediate data, an IO module
6
including an I/O circuit for externally transmitting and receiving signals including data, and a Direct Memory Access Controller (DMAC)
7
for directly accessing RAM
5
to externally transmit and receive data. These CPU core
2
, ROM
4
, RAM
5
, I/O module
6
and DMAC
7
are interconnected via an internal bus
3
.
CPU core
2
is equipped with a Debug Support Unit (DSU)
2
a
for facilitating debugging of software (program) to be executed by CPU core
2
. Debug support unit (DSU)
2
a
is connected to a DSU control signal line connected to a pin terminal
10
, a CPU event notifying signal line connected to a pin terminal
11
for externally notifying that the CPU attains a specific internal state, and to a signal line connected to a pin terminal
12
for tracing an operation state of the CPU.
LSI with CPU
1
further includes a debugging multiplexer (MUX)
18
for connecting one of IO module
6
and internal bus
3
to an I/O terminal
13
in accordance with a test mode instructing signal TP applied via a pin terminal
19
. Internal bus
3
transmits signals including data, address signals and control signals.
In LSI with CPU
1
, CPU core
2
and DMAC
7
form a bus master of internal bus
3
. This internal bus
3
is further connected to peripheral circuits such as a bus arbiter, which are not shown in the figure for simplicity reason.
In the debug operation, LSI with CPU
1
is coupled via pin terminals
10
-
12
to a DSU-adapted debug device
20
which in turn is externally arranged. DSU-adapted debug device
20
includes a controller
20
a
for controlling an operation of debug support unit (DSU)
2
a
included in CPU core
2
, and a trace data storage memory
20
b
controlled by controller
20
a
to store a CPU operation state trace signal applied from debug support unit
2
a
via pin terminal
12
. DSU-adapted debug device
20
is coupled to a computer
30
via a pin terminal
22
. Accordingly, DSU-adapted debug device
20
can control the operation of the CPU included in CPU core
2
under control of computer
30
, and can display the trace data stored in trace data storage memory
20
b
on the display screen of computer
30
.
Under the debug environment, I/O terminal
13
is coupled to a logic analyzer
40
via a probe cable
42
. Logic analyzer
40
monitors the logical levels of the signals on I/O terminal
13
.
In the normal operation, debugging multiplexer (MUX)
18
selects and couples IO module
6
to I/O terminal
13
. In the debug environment, debugging multiplexer (MUX)
18
couples internal bus
3
to I/O terminal
13
in response to activation of test mode instructing signal TP applied to pin terminal
19
. By coupling internal bus
3
to I/O terminal
13
via debugging multiplexer (MUX)
8
, the state of internal bus
3
is monitored by logic analyzer
40
in the debug environment. During debugging of software running on LSI with CPU
1
, it is necessary to externally monitor signals that are output onto internal bus
3
in accordance with the software executed by CPU core
2
, to determine whether this software is executed accurately or not. Debugging multiplexer (MUX)
18
is provided for the purpose of externally monitoring the signal value on internal bus
3
.
In the debug operation, DSU-adapted debug device
20
applies control signals to debug support unit
2
a
via DSU control pin terminal
10
, and the CPU core
2
executes the instruction under the control of these control signals. Debug support unit
2
a
monitors the operation state of the CPU included in CPU core
2
, and applies a CPU event notifying signal to DSU-adapted debug device
20
via pin terminal
11
when the CPU attains a specific internal state specified at the time of debugging. In DSU-adapted debug device
20
, when the CPU event notifying signal received via pin terminal
11
from debug support unit
2
a
becomes active, controller
20
a
applies a write instruction to trace data storage memory
20
b
, and the CPU operation trace information applied via pin terminal
12
from debug support unit
2
a
is stored therein. The CPU operation trace information stored in trace data storage memory
20
b
is applied to computer
30
via pin terminal
22
for display on the computer screen or the like.
Under the debug environment, debugging multiplexer (MUX)
18
couples I/O bus
3
to I/O pin
13
, and logic analyzer
40
monitors the signal values on internal bus
3
via I/O pin
13
and debugging multiplexer (MUX)
18
. The result of monitoring is displayed on a display screen of logic analyzer
40
.
An operator checks information displayed on the display screen of computer
30
and the display screen of logic analyzer
40
, and determines whether the CPU core
2
operates correctly to execute the specified instructions or not.
When an abnormality is found, the instruction causing the abnormality is identified based on the CPU operation trace information, and the debug is executed.
In this LSI with CPU
1
, the bus master of internal bus
3
is CPU core
2
and direct memory access controller (DMAC)
7
. When the CPU of CPU core
2
is performing arithmetic processing, direct memory access controller (DMAC)
7
accesses random access memory (RAM)
5
without adversely affecting the arithmetic operation, and executes data transfer with an external common memory or a logic/processor. In this LSI with CPU
1
, the CPU included in CPU core
2
and direct memory access controller (DMAC)
7
operate in parallel with each other. Debugging relating to the parallel operation of CPU core
2
and direct memory access controller (DMAC)
7
is very important for ensuring integrity of data.
In this debug environment for the conventional LSI with CPU shown in
FIG. 15
, the signal values on internal bus
3
are displayed on the screen of logic analyzer
40
, and the information relating to the operation state of the CPU included in CPU core
2
is displayed on the screen of computer
30
. Logic analyzer
40
and computer
30
operate independently of each other. Therefore, the operation state information of the CPU included in CPU core
2
cannot be displayed on the same time base as the signal values on the internal bus. Therefore, it is difficult to correlatingly analyze the operation of CPU included in CPU core
2
and the operation state of the direct memory access controller (DMAC). Accordingly, it is extremely difficult to perform the debugging relating to the parallel operation of the CPU and the direct memory access controller (DMAC).
Since logic analyzer
40
is used, it is necessary to connect probe cable
42
to I/O pin terminals
13
, and therefore I/O pin terminals
13
must be arranged on a circuit board. Therefore, logic

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