Flash memory device with cell current measuring scheme using...

Details Flash memory device with cell current measuring scheme using... Flash memory device with cell current measuring scheme using...

2001-11-26

2003-11-25

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S201000, C365S185090, C365S185110

Reexamination Certificate

active

06654290

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 2001-000214, filed on Jan. 3, 2001, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention generally relates to a flash memory device and, more particularly, to a flash memory device that can measure a flowing current through a memory cell.
BACKGROUND OF THE INVENTION
Typical construction of the cell (or cell transistor) of a flash memory device is shown in FIG.
1
. Source
3
and drain
4
, each being formed of a N+ diffused region in P+ semiconductor substrate (P-sub)
2
, are separated from each other through a channel region that is defined in the substrate
2
. Floating gate
6
is formed over the channel region through a thin insulating film
7
. Another insulating film
9
on the floating gate
6
isolates the control gate
8
from the floating gate
6
. The source
3
, drain
4
, control gate
8
, and substrate
2
are each connected to their corresponding voltage sources Vs (source voltage), Vd (drain voltage), Vg (gate voltage), and Vb (bulk voltage), for programming, erasing, and reading operations.
Table 1 shows levels of voltages used in programming, erasing, and reading.
TABLE 1
Operation Mode
Vg
Vd
Vs
Vb
Programming
  9 V
5 V
0 V
0 V
Erasing
 
−9 V
Floating
Floating
9 V
Reading
4.5 V
1 V
0 V
0 V
In programming, as is well known, a selected memory cell is programmed by means of hot electron injection between the channel region and floating gate, in which the source and substrate are held at a ground voltage, a high voltage (Vg=9V) is applied to the control gate, and a voltage suitable for inducing the hot electrons therein is applied to the drain. After programming, a threshold voltage of the selected memory cell is increased due to a deposition of electrons. In order to read data from the programmed cell, a voltage of about 1V is applied to the drain, a power source voltage (e.g., 4.5V) is applied to the control gate, and the source is held at the ground voltage. Since the increased threshold voltage of the programmed memory cell acts as blocking potential for a gate voltage during a read-out operation, the programmed cell is sensed as an “off-cell” by a sense amplifier circuit (not shown).
Erasing a memory cell is accomplished by a conducting F-N (Fowler-Nordheim) tunneling effect. To induce the F-N tunneling, the control gate is coupled to a high negative voltage of about −9V and the substrate is coupled to a positive voltage of about 9V. In this case, the drain is conditioned at a high-impedance state (or a floating state). A strong electric field induced by such voltage bias conditions, between the control gate and the substrate, causes electrons to be moved into the source. The erased cell has a lower threshold voltage than before, and is sensed as an “on-cell” by the sense amplifier circuit.
The threshold voltage of a programmed/erased memory cell can be measured (or determined) by measuring an amount of a current that flows through a memory cell when applying the voltages Vd and Vg corresponding to the drain and gate of the cell transistor. A conventional flash memory is shown in FIG.
2
.
Referring now to
FIG. 2
, a NOR-type flash memory device includes memory cell array as data storage area. The memory cell array is made of a plurality of array blocks
10
a
,
10
b
, . . . , and
10
c
determined with input/output structure (or each corresponding to input/output pads). Each of the array blocks
10
a
,
10
b
, . . . , and
10
c
has a plurality of memory cells that are arranged in a matrix of rows (or wordlines) WL
0
-WLm and columns (or bitlines). Each of the memory cells is connected between a corresponding bitline and source line S/L, and is driven by a potential of a corresponding wordline connected to a row decoder
12
. In other words, memory cells of each row are coupled to a corresponding bitline.
The row decoder
12
selects one of the wordlines WL
0
-WLm that are arranged through each of the array blocks
10
a
,
10
b
, . . . , and
10
c
. The row decoder
12
supplies the selected wordline to a wordline voltage VWL that is received from one of a high voltage charge pump
16
, a read pump
18
, and an external voltage pad
20
through a wordline voltage selector circuit
14
. The high voltage charge pump
16
generates a wordline voltage required in a programming operation, and the read pump
18
generates a wordline voltage required in a reading operation. In a test operation mode to measure a current flowing through a memory cell (hereinafter referred to as “cell current”), an external voltage is applied through the external voltage pad
20
.
The NOR-type flash memory device includes column selectors
24
a
,
24
b
, . . . , and
24
c
each corresponding to array blocks
10
a
,
10
b
, . . . , and
10
c
that are coupled to corresponding data lines DLa, DLb, . . . , and DLc, respectively. For simplicity, a typical construction associated with only one column selector will be explained herein. However, it is understood that constructions associated with the other columns will be identical thereto. The column selector
24
a
selects one column of the corresponding array block
10
a,
and connects the selected column to the corresponding data line DLa. A sense amplifier
28
a
, a write driver
30
a
, and a path gate
38
a
are commonly connected to the data line DLa.
For a reading operation, the sense amplifier
28
a
senses and amplifies data of the memory cell through the selected column by the corresponding column selector
24
a
, and transmits the sensed data to a corresponding input/output pad
36
a
through a corresponding data output buffer
32
a
. For a programming operation, the write driver
30
a
transfers write (or program) data, supplied from the corresponding input/output pad
36
a
, to the selected column through the corresponding data input buffer
34
a
. High level write data at a high voltage Vpb is supplied from the high voltage charge pump
26
and generates a drain voltage (or bitline voltage) required in the programming operation. The path gate
38
a
is made of an NMOS transistor connected between a corresponding data line and an input/output pad, as shown in FIG.
3
. The NMOS transistor is switched in accordance with a control signal CurMeas that indicates a test operation mode to measure a cell current.
In the test operation mode, any wordline is selected by the row decoder
12
, and one bitline of the respective array blocks
10
a
,
10
b
, . . . , and
10
c
is selected by the column decoder
22
and the corresponding column selector. An external voltage, which is supplied through the external voltage pad
20
, is supplied to the selected wordline. Data bits, each being transferred to corresponding input/output pads, are transferred to the selected bitline of the array blocks
10
a
,
10
b
, . . . , and
10
c
through the corresponding path gates
38
a
,
38
b
, . . . , and
38
c
and the data lines DLa, DLb, . . . , and DLc. Under such a condition, the current flowing through a memory cell to be tested at each array block is externally measured.
In the conventional flash memory device, path gates must be constructed corresponding to the number of sense amplifiers or write drivers. This causes an undesirable increase in a chip size of the flash memory device.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a flash memory device capable of measuring a cell current with the use of a write drive.
According to one aspect of the invention, a non-volatile semiconductor memory device includes an array of memory cells that are arranged in a matrix of bitlines and wordlines. The bitlines are divided into a plurality of groups each corresponding to input/output pads. The non-volatile semiconductor memory device further includes a column selection circuit, a first voltage switch circuit, and a plurality of write drivers. The column selection circuit selects one of the bitlines of the respective groups. The first vo

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