Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-23
2003-06-10
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S345000
Reexamination Certificate
active
06576966
ABSTRACT:
FIELD OF USE
This invention relates to insulated-gate field-effect transistors (“FETs”)and, in particular, to an insulated-gate FET having improved operating characteristics.
BACKGROUND
Field-effect transistors of the MOS type are currently the principal active vehicle in very-large-scale integrated (“VLSI”)circuits, particularly in CMOS circuit implementations. Device miniaturization has brought the horizontal FET dimensions down to the 0.5 to 2.0 &mgr;m range, and the dielectric thickness under the gate electrode down to the 0.015 to 0.040 &mgr;m range. The lower ends of these ranges are characteristic of digital integrated circuits operated at a supply voltage of 5 or 3.3 V, while the upper ends of these ranges are characteristic of analog integrated circuits operated at a supply voltage in excess of 10 V.
FIG. 1
illustrates a basic n-channel MOS transistor
10
. Heavily doped n-type source
12
and drain
14
are situated in a p-type silicon substrate
16
. An n-type polysilicon gate electrode
18
is insulated from a channel region
20
by oxide gate dielectric layer
22
.
The maximum electric field in the silicon in the vicinity of drain zone
14
occurs at the intersection
23
of the drain pn junction and the silicon/silicon oxide interface. One of the earliest observed limitations of the conventional FET structure in
FIG. 1
was that the (maximum) electric field at point
23
was related to the electric field across oxide gate dielectric
20
rather than to the field across the bulk portion of the drain junction depletion region. To a first approximation, the breakdown voltage V
DB
of the drain junction at values of the gate voltage V
G
below the threshold level is determined from the following pair of equations for an n-channel device:
E
MAX
=
α
(
V
DB
-
V
G
X
0
)
(
1
)
E
MAX
=
E
CRIT
(
2
)
where E
MAX
is the maximum field in silicon at the drain junction, E
CRIT
is the maximum field at breakdown in silicon (customarily referred to as “critical field”), x
0
is the gate oxide thickness, and &agr; is a factor in the vicinity of ⅓. E
CRIT
is assumed to be constant. See Grove, “Effect of Surface Fields on the Breakdown Voltage of Planar Silicon p-n Junctions,”
IEEE Trans. Elec. Devs
., March 1967, pages 157-162.
Further, drain junction breakdown voltage V
DB
increases as the background (substrate) dopant concentration decreases. This is a second-order effect not reflected in simplified Eq. 1. The V
DB
increase with decreasing background dopant concentration originates from a slow variation of the critical field E
CRIT
as a function of the background dopant concentration and is present, to different extents, at any gate oxide thickness. Another second-order effect not reflected in Eq. 1 is that breakdown voltage V
DB
decreases as the depth of the drain junction decreases.
The values of drain breakdown voltage V
DB
determined by the thin gate oxides typically used in VLSI circuits are less than what the gate length, background concentration, and the drain junction curvature could support with thicker gate oxides.
More important than the breakdown voltage reduction associated with the insulated gate structure in
FIG. 1
is that avalanche breakdown of the drain junction is localized at the upper silicon surface. This situation is customarily referred to as surface breakdown and impairs device reliability due to associated hot-carrier effects.
First consider the condition in which the gate voltage V
G
is below the threshold level so that FET
10
is turned off. Under the high electric field present where drain
14
terminates channel
20
, the holes created by impact ionization in an n-channel device can acquire sufficient energy (become sufficiently “hot”) to surmount the energy barrier between the semiconductor (channel
20
) and gate dielectric
22
. Some of the hot holes jump (get injected) into gate dielectric
22
where they may become trapped. This causes threshold voltage instability and/or transconductance degradation.
Similar effects take place when the transistor is turned on—i.e., gate voltage V
G
is above the threshold level—and drain
14
approaches an avalanche breakdown condition in which electron-hole pairs are generated. In this case, the hot electrons are injected into gate oxide
22
while the holes flow into substrate
16
. Also, avalanche-generated holes flow into substrate
13
biasing it positively with respect to source
12
. The source-substrate junction becomes forward biased. This causes the drain current to increase abnormally and ultimately leads to a premature breakdown condition. Such hot-carrier effects are more critical in n-channel FETs than in p-channel FETs because the impact ionization rates of electrons are one to two orders of magnitude higher than those of holes.
One solution to the above problems is to reduce the level of drain doping at the upper silicon surface where the drain terminates the channel by using a lightly doped drain (“LDD”)process. See Ogura et al, “Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor,”
IEEE Trans. Elec. Devs
., August 1980, pages 1359-1367. Also see Ogura et al, “Elimination of Hot Electron Current by the Lightly Doped Drain Structure,” IEDM, 1981, pages 651-654.
The LDD solution, illustrated by n-channel MOS transistor
24
in
FIG. 2
, is widely used in current VLSI products. The drain consists of main portion
14
and a more lightly doped drain extension
26
that extends slightly under gate electrode
18
. Fabrication of the LDD structure entails ion implanting drain extension
26
in a self-aligned manner, followed by implantation and drive-in diffusion of heavily doped main drain portion
14
. The lateral edge of main drain portion
14
is separated laterally from the lateral edge of drain extension
26
and gate electrode
18
by providing an insulating spacer
27
along the drain side of gate electrode
18
during the time between the two implantations. Spacer
27
and gate electrode
18
serve as an implant shield during the second implant so as to control the location of LDD extension
26
relative to main drain portion
14
.
The source of the LDD FET is formed simultaneously with the drain and is typically configured in the same way. As shown in
FIG. 2
, the source consists of main source portion
12
and a more lightly doped source extension
28
. For reasons of fabrication simplicity and also source/drain symmetry, the LDD implant is applied identically to the source to form source extension
28
. An insulating spacer
29
provided along the source side of gate electrode
18
acts to control the location of source extension
28
relative to main source portion
12
.
The LDD solution is effective when the surface doping concentration of LDD extension
26
is in the vicinity of 10
17
atoms/cm
3
, down from 10
20
atoms/cm
3
in main drain portion
14
. This is illustrated in
FIG. 3
taken essentially from either of the articles of Ogura et al, cited above. Lateral distance in
FIG. 3
is measured from the left-hand edge of FIG.
2
. In this regard, note that
FIG. 3
is presented at a different scale than FIG.
2
.
The LDD structure typically results in a thirty-fold reduction in substrate current compared to FETs using a conventional drain design of the type shown in FIG.
1
. The improvement achieved with the LDD structure is explainable using the simplified model of Eq. 1. The thickness of easily depleted LDD extension
26
effectively adds (as an insulator) to the thickness of gate oxide
22
, thereby reducing the electric field in the silicon along the drain surface region.
Unfortunately, the large reduction in dopant level around the drain end of channel
22
in the LDD structure of
FIG. 2
cannot be accommodated at the source end without degrading the current drive capability of the device due to increased series source resistance. Accordingly, CMOS VLSI processes in current use typically rely on a compromise LDD surface doping concentration in the vicinity of 10
18
atoms/cm
3
Meetin Ronald J.
National Semiconductor Corporation
Prenty Mark V.
Skjerven Morrill LLP
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