Semiconductor memory device and its method of manufacture

Details Semiconductor memory device and its method of manufacture Semiconductor memory device and its method of manufacture

2002-02-06

2003-06-24

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Schottky barrier

With means to prevent edge breakdown

C257S127000, C257S170000, C257S409000, C257S452000, C257S602000, C438S257000, C438S223000, C438S570000

Reexamination Certificate

active

06583486

ABSTRACT:

CROSS REFERENCE
This application claims benefit and priority of Korean Patent Application No. 2001-5866, filed on Feb. 7, 2001, under 35 U.S.C. §119, the entirety of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a guard ring.
2. Description of Related Art
In a semiconductor memory device, it may be desirable to prevent noise of an external signal from adversely affecting its performance. For example, an external signal may propagate from a terminal to a pad of the semiconductor memory device. If the signal carries a negative undershoot to the pad, the negative undershoot may generate minority carriers, e.g., electrons, in the semiconductor material of the memory device. Such minority carrier noise (e.g., electrons) might then reach and adversely affect memory cells of the memory device.
To avoid such problems, an n-well may be formed in a ring shape surrounding the array of memory cells to serve as guard ring for absorbing minority carriers that may be in the substrate. For example, the guard ring may collect electrons that may be generated by a negative undershoot signal. By collecting such noise electrons, the guard ring prevents the noise electrons from reaching the memory cells of the memory device so that data of the memory cells can remain stable.
Japanese Patent Laid-Open Publication No. hei 6-85203 describes a semiconductor memory device with n-well regions to suppress such noise. The semiconductor memory device includes an I/O circuit region, a periphery circuit region and a memory cell region. In the I/O circuit region, an n-well is formed to surround p-well portions of the I/O circuit region. The n-well of the I/O circuit region is provided a depth deeper than that of the n-well for the periphery circuit region. Similarly, an n-well is formed to surround p-well portions of the memory cell region and is provided a depth deeper than that of the n-wells of the periphery circuit region.
However, for the semiconductor memory device of Japanese Patent Laid-Open Publication No. hei 6-85203, problems may exist with provision of its protective n-wells if the memory cell regions are to become more dense. The n-wells of this memory device may adversely affect an isolation margin (and process margin) between wells of the memory cell region when such designs evolve to higher levels of integration. Accordingly, they can limit the level of integration that might otherwise be available for the memory device.
Additionally, in order to surround the side and bottom portions of the p-wells, the depth of the p-wells is kept less than that of the surrounding n-well. As a result, the push for higher levels of integration will require further reductions in depth for the p-wells, which may affect increased resistance and an increased risk for latch-up. Additionally, the isolation between n+ dopant regions (e.g., source and drain regions of a NMOS transistor) that may be formed in the p-well might also be reduced.
In order to overcome some of the above problems, a semiconductor memory device may have an n-well formed for the periphery circuit region, which will allow for improved levels of integration and enhanced densities for the memory cell region.
FIG. 1
is a simplified plan view illustrating a semiconductor memory device with a guard ring. The semiconductor memory device includes a memory cell region
101
and a periphery circuit region
102
. In
FIG. 1
, the separate memory and periphery regions may be delineated by the one-dot line. Memory cell region
101
includes n-wells
110
, p-wells
120
and a plurality of unit cells
141
. In
FIG. 1
, a dotted line delineates the unit cells
141
. As shown in this embodiment, the cells may be arranged in a matrix pattern for an array
140
. Also, the periphery circuit region
102
may include p-well
125
and n-well
130
. N-well
130
may be formed to surround sides of cell array
140
of the memory cell region
101
and may serve as a guard ring to collect electrons that might be generated within the substrate by, e.g., a negative undershoot signal.
In one example, unit cell
141
may comprise an SRAM cell, which may be classified as a full CMOS cell, a high road resistor (HRL) or thin film transistor (TFT) cell as determined in accordance with the type of load. The full CMOS cell, which is more common, uses a bulk PMOS transistor for its load element and comprises two bulk PMOS transistors and four bulk NMOS transistors. Thus, referencing
FIG. 1
, the memory cell region
101
for the conventional semiconductor memory device may include n-wells
110
for the formation of bulk PMOS transistors and p-well regions
120
for the formation of bulk NMOS transistors.
The n-wells
110
,
130
may be formed in respective regions of memory cell region
101
and the periphery circuit region
102
, respectively. These n-wells, for the conventional device, are formed at the same time during a single ion implantation process via a common mask. Such exemplary process for manufacturing a semiconductor memory device of
FIG. 1
, is explained below with reference to
FIGS. 2A
,
2
B,
3
A, and
3
B.
FIGS. 2A and 2B
are cross-sectional views taken along line II—II of
FIG. 1
, and
FIGS. 3A and 3B
are cross-sectional views taken along line III—III of FIG.
1
.
Referring to
FIGS. 2A and 3A
, a first mask pattern
151
is formed so as to leave exposed portions of, e.g., a p-type semiconductor substrate
100
. The exposed portions will correspond to the desired regions for the n-wells. N-type impurities are then ion-implanted into the exposed areas to form n-wells
110
in the memory cell region
101
and n-well
130
in the periphery circuit region
102
as defined by mask pattern
151
. As previously described, the regions of n-well
110
may be used to form PMOS transistors in the memory cell region
101
, while the regions of n-well
130
may surround the array of cell
140
of the memory cell region
101
to serve as a guard ring. At this point, PMOS transistors may also be formed on the n-well
130
of the periphery circuit region. After forming n-wells
110
,
130
, the first mask pattern
151
may be removed.
Sequentially, with reference to
FIGS. 2B and 3B
, a second mask pattern
152
may be formed and patterned to expose portions of the semiconductor substrate
100
where p-wells may be formed. P-type impurities may then be ion-implanted into exposed regions of the substrate to form p-wells
120
in the memory cell region
101
and p-wells
125
in the periphery circuit region
102
as defined by the mask pattern
152
. The p-wells
120
of the memory cell region may be located between two neighboring n-wells
110
, and the p-wells
125
of the periphery region may be formed on both sides of n-well
130
.
As described above, n-well
130
may act as a guard ring to surround a side portion of the memory's cell array
140
(FIG.
1
). But given that n-wells
110
and
130
are formed by the same process step, i.e., through a common one-time ion implantation process that uses a common mask, the n-wells
110
and
130
will have substantially the same depth.
To assist electron collection, the n-well for the guard ring, with reference to the cross-sectional view of
FIGS. 4-5
, is to effect an electric field through a depletion region and across a PN junction that are formed between the n-well and p-well.
Further referring to
FIG. 5
, n-well
130
and p-well
125
meet to form a PN junction. A depletion region DR results across the interface of p-well
125
and n-well
130
, which may be centered about the PN junction or surface JS. An electric field is formed across the depletion region and may be directed from the n-well
130
toward the p-well
125
. Since electrons
126
have a negative polarity, they move in a direction opposite an electric field. Accordingly, electrons
126
may move from regions of p-well
125
to n-well
130
to be collected by the n-well.

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