Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2000-12-27
2003-12-02
Ellis, Kevin L. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
Reexamination Certificate
active
06658544
ABSTRACT:
BACKGROUND
The present invention relates to memory, and more particularly, but not exclusively relates to techniques to asynchronously operate a synchronous memory.
Frequently, the devices of a digital system are synchronized by a periodic clock signal. Such systems sometimes include a synchronous memory that utilizes the clock signal to time various internal operations, including the recognition of a valid memory address input. Because a transition in the clock signal can reach different devices at slightly different times, a race condition can sometimes arise. Extreme temperature, power supply voltage levels, and/or other operational extremes can exacerbate these differences. To address such race conditions, device operation can be slowed to improve synchronicity.
Another approach utilizes asynchronous memory devices. An asynchronous memory often includes circuitry to detect a transition in the input memory address to determine address validity instead of relying on a clock signal input as in the case of a synchronous memory. In other arrangements, memory devices are proposed that operate in both synchronous and asynchronous modes. These dual-mode designs are usually of a more complex nature than single-mode designs. U.S. Pat. Nos. 5,107,465 to Fung et al. and U.S. Pat. No. 5,384,737 to Childs et al. are cited as additional sources of background information concerning such memory devices.
It is often desirable to utilize proven designs as much as possible when designing a new circuit—particularly for high device count circuits such as an integrated circuit memory. This desire, coupled with needs for both synchronous and asynchronous memories, indicates a demand to utilize one memory type, such as a synchronous memory, to provide another memory type, such as an asynchronous memory, without requiring a large degree of redesign of the first memory type.
SUMMARY OF THE INVENTION
One embodiment of the present invention is a unique technique to asynchronously operate a synchronous memory. Other embodiments of the present invention include unique methods, systems, and apparatus to provide an asynchronously accessible memory.
Another embodiment includes a synchronous memory and control circuitry coupled to this memory to asynchronously access it. The synchronous memory can include a clock circuit, and the control circuitry can be responsive to one or more address inputs to generate a control signal that is provided to this clock circuit. In a further form, the synchronous memory is operable to provide the control circuitry at least one signal to variably time asynchronous access operations.
Still another embodiment includes specifying an asynchronous memory design with a number of macros, selecting at least one of the macros to include a synchronous memory in the asynchronous memory design, and selecting at least another of the macros to include circuitry in the asynchronous memory design to asynchronously operate the synchronous memory. Collectively, the synchronous memory and the circuitry are arranged to provide an asynchronous memory according to the asynchronous memory design.
Yet another embodiment of the present invention comprises providing a synchronous memory including a clock input, coupling the clock input to circuitry responsive to one or more address inputs, and asynchronously operating the synchronous memory with the circuitry through the clock input.
A further embodiment of the present invention is a system that includes an address bus, a synchronous memory coupled to the address bus, and circuitry including a transition detection circuit and a monostable multivibrator. The detection circuit includes one or more inputs coupled to the address bus, and the monostable multivibrator circuit includes a trigger input coupled to the detection circuit. The monostable multivibrator circuit further includes an output coupled to the synchronous memory. This circuitry can be used to asynchronously operate the synchronous memory.
Accordingly, one object of the present invention is to provide a unique technique to asynchronously operate a synchronous memory.
Another object of the present invention is to provide a unique method, system, or apparatus directed to an asynchronously accessible memory.
Further objects, embodiments, forms, features, benefits, and advantages of the present invention shall become apparent from the description and figures included herewith.
REFERENCES:
patent: 4337525 (1982-06-01), Akatsuka
patent: 4417328 (1983-11-01), Ochii
patent: 4615017 (1986-09-01), Finlay et al.
patent: 4849904 (1989-07-01), Aipperspach et al.
patent: 4872143 (1989-10-01), Sumi
patent: 5029135 (1991-07-01), Okubo
patent: 5107465 (1992-04-01), Fung et al.
patent: 5187779 (1993-02-01), Jeddeloh et al.
patent: 5191657 (1993-03-01), Ludwig et al.
patent: 5357613 (1994-10-01), Cantrell et al.
patent: 5384737 (1995-01-01), Childs et al.
patent: 5625796 (1997-04-01), Kaczmarczyk et al.
patent: 5698876 (1997-12-01), Yabe et al.
patent: 5727005 (1998-03-01), Le et al.
patent: 5883854 (1999-03-01), Becker
patent: 5930197 (1999-07-01), Ishibashi et al.
patent: 5982680 (1999-11-01), Wada
patent: 6044024 (2000-03-01), Barth et al.
patent: 6047361 (2000-04-01), Ingenio et al.
patent: 6075830 (2000-06-01), Piirainen
patent: 6097663 (2000-08-01), Watanabe et al.
patent: 6115783 (2000-09-01), Murayama
patent: 6178138 (2001-01-01), Derbenwick et al.
Ellis Kevin L.
Zawilski Peter
LandOfFree
Techniques to asynchronously operate a synchronous memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Techniques to asynchronously operate a synchronous memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Techniques to asynchronously operate a synchronous memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3130133