Testing a bus coupled between two electronic devices

Details Testing a bus coupled between two electronic devices Testing a bus coupled between two electronic devices

2000-03-10

2003-06-03

Chung, Phung M. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Transmission facility testing

C714S715000

Reexamination Certificate

active

06574758

ABSTRACT:

BACKGROUND
U.S. Pat. No. 5,228,042 (see abstract) describes using pseudo random data to test a bus between two electronic devices. Specifically a “linear feedback shift register” (abbreviated “LFSR”) generates a periodic sequence of pseudo random data that is used to test transmission paths between circuits. A second LFSR synchronizes to the transmitted test data after being provided with a seed value corresponding to a transmitted data word. After synchronization, the second LFSR is set to a free running mode and independently generates a pseudo random sequence of patterns corresponding to the sequence generated by the first LFSR. A comparator compares the pseudo random data generated by the second LFSR with the pseudo random data received from the transmission paths. If a mismatch occurs, a signal indicating an error condition is asserted. Both LFSRs receive the same clock signal (via line 18 as described at column 3, lines 60-65 and illustrated in FIG.
1
).
See also the following: U.S. Pat. Nos. 5,202,625, 5,228,042, 5,416,409, 5,423,050, 5,473,617 and 5,717,701.
SUMMARY
In one embodiment, a bus having multiple lines and coupled between two electronic circuits (e.g. that communicate at double data rate abbreviated as “DDR”) is tested by transmitting from a first circuit a test signal, and recognizing receipt of the test signal in a second circuit. Specifically, the second circuit compares a version of test signal received from the bus with a local copy of the test signal. If the received version does not match the local copy, a comparator in the second circuit indicates failure of receipt of the test signal.
In this embodiment, a sequence (over time, e.g., on successive edges of a clock signal in the case of DDR) of test signal is used to test the bus, and the second circuit specifically identifies the test signal that failed (from among other signals in the sequence) by generating an error signal. Such an error signal can simply indicate the location of the failed test signal in the sequence. In one implementation, the second circuit maintains a registrer, and bits in the register are accessed using the identity of the test signal as the address, and the values of the bits are set by the comparator.
Prior to transmission of the sequence, an indication that the sequence is about to start can be provided in any number of ways. In one implementation, the first circuit indicates to the second circuit that the sequence is about to start by transmitting a predetermined signal (also called “start signal”) on the bus. The second circuit recognizes the start signal, and thereafter begins to process the sequence
In one implementation, one or more test signals in the sequence are identical to each other except in just the location of a predetermined pattern of bits (i.e. bits having a predetermined value). In one example, a test signal is formed by assigning to a set of four bits the value 1010, and to all remaining bits the value 1. Such a predetermined pattern may be located in the beginning, middle or end of three test signals of such a sequence.
One example of a predetermined pattern tests (using just one test signal that includes bit pattern 010) the relationship between a line carrying a bit of value 1 with two adjacent lines carrying bits of value “0,” thereby to identify the line as defective if the bit pattern 000 is received for example. Therefore, if there is crosstalk between two adjacent lines, such lines are specifically identified when the received version of the pattern differs from the pattern that was transmitted (as determined from a locally-generated copy of the transmitted pattern).
In one implementation, location of the predetermined pattern is changed in each test signal of such a sequence, to test all lines of the bus. Any sequence of test signals of the type described herein (i.e. the test signals can be in any order relative to one another) can specifically identify any line that is defective. In one variant of the above-described example, the predetermined pattern is shifted (to the left or to the right depending on the implementation) one position at a time so as to sequentially generate test signals that test each line of the bus.
So, almost all test signals of such a sequence are derived by simply shifting (e.g. to the left) the bits of a predetermined pattern in a sequential manner. Therefore, in one embodiment, each circuit includes a shifter that shifts the predetermined pattern to obtain the sequence of test signals, and such a sequence is called a “walking pattern.” In a “walking pattern” sequence of the type described herein, location of a failed test signal in the sequence automatically identifies the line having the failure (because of the single bit difference in position between two successive test signals of the sequence).
Instead of generating pseudo random patterns of the type described in the above-discussed U.S. Pat. No. 5,228,042, the circuitry of the type described herein generates a sequence of test signals that are known in advance. Moreover, the sequence specifically identifies which of the one or more lines in the bus is/are faulty, unlike U.S. Pat. No. 5,228,042. Furthermore, sequences of the type described herein can be obtained by a simple shift operation in each of the two devices, thereby to eliminate complex circuitry otherwise required to generate pseudo random patterns as discussed in U.S. Pat. No. 5,228,042.


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“DDR SDRAM Boldly Charges Ahead”, JEDEC Solid State Technology Division, Sep. 22, 1998, 2 pp.
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144 Pin DDR SGRAM SO-DIMM Family, JEDEC Standard No. 21-C, Feb. 22, 1999 and Apr. 14, 1999, pp. 4.5.9-1-4.5.9-10.

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