Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
Reexamination Certificate
1999-12-28
2003-10-14
Kim, Kenneth S. (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Scoreboarding, reservation station, or aliasing
C712S023000, C712S218000
Reexamination Certificate
active
06633970
ABSTRACT:
FIELD
The invention generally relates to processors, and in particular to RAT state history recovery mechanism.
BACKGROUND
In some current processors, instructions are decoded into one or more micro-operations (uops), and each uop is loaded into a re-order buffer (ROB) to await scheduling for execution. A register alias table (RAT) is provided for storing a mapping or aliasing between logical registers and physical registers. The physical registers include the real register file (RRF) for storing retired data, and include the ROB for storing temporary or unretired data. After a uop is executed, the execution result is temporarily stored in the ROB. Uops are retired (or committed to architectural state) in order by physically moving the execution result (data) from the ROB to the RRF, and updating a pointer in the RAT for the corresponding logical register. An example of this type of processor is described in U.S. Pat. No. 5,727,176. However, this configuration has limitations. As execution units and other portions of the processor increase in speed, it becomes more difficult to physically move the data at retirement from the ROB to the RRF. A better technique is needed to keep track of temporary and retired data in the processor.
U.S. Pat. No. 5,197,132 (the '132 patent) discloses a register mapping system having a log containing a sequential listing of registers that were changed in preceding cycles for post-branch recovery. A register map includes a predicted map and a backup map, with each map storing a mapping to the physical home of each logical register. Muxes are provided in the '132 patent for selecting between the two maps for use. However, this arrangement is cumbersome and requires significant silicon due to the muxing between the two maps, and because data output paths are connected to each map. Moreover, the mapping circuit in the '132 patent is inflexible as it requires the backup map to maintain a particular minimum distance (e.g., 20 clock cycles) behind the predictive map to allow the processor to confirm that the first instruction does not cause an event that requires the register map to be backed up to an earlier state using the backup map. Thus, the '132 patent discloses a restrictive and inflexible approach. As a result, there is a need for a more flexible and effective technique for keeping track of the temporary and permanent data in the processor.
SUMMARY
According to an embodiment of the present invention, an apparatus is provided for allowing a processor to recover from a failure of a predicted path of instructions. The apparatus includes a plurality of physical registers, each physical register to store either architectural data or speculative data. The apparatus also includes a primary array a primary array to store a speculative state of the processor including mappings from logical registers to physical registers. The apparatus also includes a buffer coupled to the primary array to store information identifying which physical registers store architectural data and which physical registers store speculative data.
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Boggs Darrell D.
Clift David W.
Sager David J.
Intel Corporation
Kim Kenneth S.
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