Optimized routing strategy for multiple synchronous bus groups

Details Optimized routing strategy for multiple synchronous bus groups Optimized routing strategy for multiple synchronous bus groups

2000-02-25

2003-12-09

Ray, Gopal C. (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

C710S104000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06662250

ABSTRACT:

BACKGROUND
1. Field of the Invention
The present disclosure relates to signal routing in printed circuit boards and, in particular, to a routing strategy for multiple synchronous bus groups.
2. Description of the Related Art
Most computer systems include a number of components such as microprocessors and memory devices that are mounted to a multi-layered printed circuit board (PCB). The PCB may include multiple power, ground, and signal layers. The components are packaged in a variety of package types such as dual in-line packages (DIPs), quad flat packs (QFPs), pin grid arrays (PGAs), and ball grid arrays (BGAs). PGAs and BGAs have become popular package types since they allow for a high number of terminals on each package. The terminals are located over the entire bottom surface or a substantial portion of the surface of the device as illustrated by the terminal footprint of an exemplary 256 pin BGA package
10
in FIG.
1
A.
PGAs are mounted to a PCB by inserting a plurality of pins that extend from the bottom surface of the package into corresponding sockets on, or through-holes in, the PCB. A BGA is essentially the same as a PGA except that the BGA has solder balls for soldering to corresponding pads on the surface of the PCB.
The terminals of PGAs and BGAs generally include multiple power, ground, and signal terminals. The signal terminals include data terminals, address terminals, clock terminals, control terminals as well as other signal terminals. Buses connect to the data, address, and clock terminals of the various devices. A bus generally refers to a collection of data lines and/or address lines. For example, one or more data and address buses may be used to connect several microprocessors and/or memory chips on a single PCB. If the data lines or address lines are synchronized using one or more non-common synchronous clock signals or strobes, as they are generally referred to, the bus is referred to as a synchronous bus. Synchronous buses are well known in the art.
FIG. 1B
shows a conventional routing method used to route a bus between two or more BGA (or PGA) packages. One disadvantage of this routing method is that it routes signals through the center regions
14
of the BGA packages
16
and
18
.
In some applications, for instance when BGA packages
16
and
18
contain microprocessors, bypass capacitors are mounted to the surface of the PCB in the center region of each BGA package. The bypass capacitors connect through vias to the underlying power and ground planes in the PCB and become distributed sources of charge to increase switching speeds when signal traces are switched between logic states. Since bus
20
is routed through the center regions
14
of BGA packages
16
and
18
, this prevents vias to the power and ground planes from being formed under the center areas
14
, near the capacitors, and instead requires the vias, and traces leading to the vias, to be formed in peripheral regions around the BGA packages
16
and
18
. These peripheral vias require longer traces to reach the capacitors and introduce undesirable parasitics and limit the effectiveness of the bypass capacitors.
Another disadvantage associated with the conventional routing method shown in
FIG. 1B
is referred to as “neckdown.” Neckdown is where the space between traces on the same layer must be reduced in order to navigate the array of vias when under, or in the immediate area of, the BGA or PGA packages in order to contact the package terminals and to not interfere with each other. For example,
FIG. 1B
shows multiple traces (bus
20
) routed on a layer of a PCB. The center-to-center distance (pitch) between the traces is very small when under the BGA package
16
or
18
so that the traces will avoid pads, vias, and each other as they traverse from the left side of BGA package
16
to the right side of the other, identical, BGA package
18
. Since the center-to-center distance between the traces is reduced, and the traces run side-by-side for a considerable distance (i.e., the entire width of the BGA package), undesirable effects such as cross-coupling occur, degrading the performance of the system. The negative effects of cross-coupling, in general, increase with the length of the neckdown area. Thus it is desirable to minimize the neckdown area.
Another disadvantage associated with conventional routing methods is that often the individual routed traces within a bus have different lengths. Since the individual traces have different lengths, the propagation delay of each line differs. This results in reduced timing margins and complicates the design of systems which use high speed synchronous buses. Further, as synchronous clock speeds continue to increase in modem devices, this problem becomes exacerbated.
Yet another disadvantage associated with conventional routing methods is that they often require a trace to make sharp turns. Sharp turns increase the parasitics (e.g., undesirable capacitive effects, reflections, etc.) of the transmission line. Such parasitics degrade the performance of the system.
What is needed is a routing strategy that ensures that traces are not routed through the center region of a package, that ensures that each trace in a bus is approximately the same length, that minimizes the length over which “neckdown” occurs, and that ensures that traces are routed without making sharp turns.
SUMMARY
An improved routing strategy is disclosed. One embodiment of a computer system includes a printed circuit board having one or more signal routing layers, a plurality of synchronous devices (e.g., microprocessors) mounted on the printed circuit board, and at least one synchronous bus, wherein the synchronous bus comprises traces that are coupled between the synchronous devices.
The traces connect to terminals of the devices such that they do not run under the central areas of the devices. This opens up the central area under each device for other circuitry, such as bypassing capacitors and their associated vias leading to various layers. Each trace in a synchronous bus is approximately the same length, and each device “sees” the same trace configuration.
The routing configuration can be easily extended to any number of synchronous devices sharing the same buses.


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M. Morris Mano, Computer System Architecture, 1982, Prentice-Hall, Inc., Second Edition, pp. 435-437.*
IEEE's definition of “circuit pack”, the Authoritative Dictionary of IEEE Standards Terms, 7 Ed. P170.*
Webopedia's definition of “bus”, http://www.webopedia.com/term/b/bus.html.*
M. Morris Mano, Computer System Architecture, 1982, Prentice-Hall, Inc., Second Edition, pp. 435-437.

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