Multi-phase EEPROM reading for network interface initialization

Details Multi-phase EEPROM reading for network interface initialization Multi-phase EEPROM reading for network interface initialization

1999-05-28

2003-11-18

Wright, Norman M. (Department: 2134)

Electrical computers and digital processing systems: support

Multiple computer communication using cryptography

Protection at a particular protocol layer

C713S002000, C713S100000, C714S003000, C714S036000

Reexamination Certificate

active

06651172

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to data processing, and more specifically, to a network interface having a system for multi-phase reading configuration data from an external EEPROM during an initialization procedure.
BACKGROUND ART
When a user turns on the power of a data processing system, such as a network controller, the hardware automatically resets to begin the process of booting. The reset signal goes to all programmable circuits. In response, these circuits initialize certain essential registers, such as system configuration registers, to place the system into a known state, from which system applications may be executed.
An external non-volatile memory, such as an electrically erasable permanent read-only memory (EEPROM), may store system-dependent configuration information, which. allows a network controller to program many of its features at power-up. The network controller comprises multiple registers programmable at power-up by reading configuration information from the EEPROM. For example, the EEPROM may store such configuration information as the size and boundary of a buffer memory, subsystem and vendor ID information, media-independent interface (MII) address, status and control information, bus interface configuration and control information, system status or activity represented by light-emitter diode (LED) indicators, full-duplex control information, etc.
As a regular EEPROM interface supports a serial data transfer, reading the EEPROM at power-up takes a substantial period of time, during which the host is not able to access the configuration information required to complete booting.
Therefore, it would be desirable to create an EEPROM reading scheme that allows the network controller to. reduce booting time.
DISCLOSURE OF THE INVENTION
The present invention provides a novel method of initializing a data processing system having registers programmable with data read from a non-volatile memory, such as an EEPROM, at power-up. The method includes segmenting the non-volatile memory into a first portion for storing priority data, and a second portion for storing regular data. The first portion is smaller than the second portion. The priority data are read from the first portion to program a first group of registers. Thereafter, the regular data are read from the second portion to program a second group of registers.
In accordance with one aspect of the invention, a host is enabled to access the first group of registers, while the regular data are read from the second memory portion. Data validity verification may be performed on the priority data after reading them from the first memory portion but before reading the regular data from the second memory portion.
The data processing system of the present invention comprises at least one first register programmable with first data read from the non-volatile memory, and at least one second register programmable with second data read from the external memory. The second data has higher length than the first data. A data reading circuit performs a multi-phase reading of the register data from the memory to read the first data before reading the second data so as to program the first register before programming the second register. The first data may have higher priority than the second data In accordance with a preferred embodiment, the non-volatile memory may be segmented into a small section for storing the first data and a larger section for storing the second data. The data reading circuit provides data validity verification on the first data before reading the second data.
In accordance with another aspect of the invention, a data processing system controlled by a host has a first and a second group of registers programmable with data read from a non-volatile memory at power-up. The first group of registers is programmable with first data relating to configuration of a bus interface that provides interface to the host. The data reading circuit reads the first data from the memory before reading second data for programming the second group of registers.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.


REFERENCES:
patent: 4841133 (1989-06-01), Gercekci et al.
patent: 5731972 (1998-03-01), Yamamoto et al.
patent: 5805882 (1998-09-01), Cooper et al.
patent: 6272584 (2001-08-01), Stancil

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