Dynamic-type semiconductor memory device having staggered activa

Details Dynamic-type semiconductor memory device having staggered activa Dynamic-type semiconductor memory device having staggered activa

1991-08-12

1994-01-04

Dixon, Joseph L.

Static information storage and retrieval

Read/write circuit

Noise suppression

36523003, 36523004, 36523008, 365233, G11C 702, G11C 800

Patent

active

052766497

ABSTRACT:
A semiconductor memory device includes a memory cell array block (1; MB1 to MB16) having a first column group (area I) and a second column group (area II). The device also includes sense amplifiers (10-1, 10-2, 10-3 . . . ) provided for each column to detect and amplify a read-out voltage on associated columns. The device further includes a control circuit (20) for activating the sense amplifiers for the first column group and the sense amplifiers for the second column group at different timings to reduce peak current in sensing operation. The control circuit operates in response to a column designating signal to activate first the sense amplifiers for the column group including a column connecting thereto a selected memory cell. The column designating signal includes an externally applied column address bit. The column address bit is supplied to the device simultaneous with row address bits in an address multiplexing memory device. The first column group (BL0, BL0, BL2, BL2) includes a plurality of bit line pairs having at least one twisted portions. The second column group (BL1, BL1) includes a plurality of bit line pairs having no or one or more twisted portion. Bit line pairs of the first column group and bit line pairs of the second column group are arranged alternately.

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Aoki et al., "An Experimental 16 Mb Dram with Transposed Data-Line Structure", Intl Solid State Circuits Conference, Feb. 1988, pp. 250-251, 391-392.
Kimura, et al., "A 65-ns 4-Mbit CMOS DRAM with a Twisted Driveline Sense Amplifier", IEEE Journal of Solid-State Cricuits, vol. SC-22, No. 5, Oct. 1987, pp. 651-656.

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