Strained Si based layer made by UHV-CVD, and devices therein

Details Strained Si based layer made by UHV-CVD, and devices therein Strained Si based layer made by UHV-CVD, and devices therein

2002-02-11

2003-11-18

Mulpuri, Savitri (Department: 2812)

Semiconductor device manufacturing: process

Formation of semiconductive active region on any substrate

C438S479000, C438S483000, C438S459000

Reexamination Certificate

active

06649492

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a method of fabricating strained Si based layers of microelectronics quality. Furthermore it relates to the transfer of such strained layers to different substrates and also onto insulating materials. The invention additionally relates to devices made in these strained Si based layers and to electronic systems built with such devices.
BACKGROUND OF THE INVENTION
Today's integrated circuits include a vast number of transistor devices formed in a semiconductor. Smaller devices are the key to enhance performance and to increase reliability. As devices are scaled down, however, the technology becomes more complex and new methods are needed to maintain the expected performance enhancement from one generation of devices to the next. This relates mainly toward the primary semiconducting material of microelectronics, namely Si, or more broadly, to Si based materials. Such materials of promise are various SiGe mixtures, and further combinations, for instance with C. One of the most important indicators of device performance is the carrier mobility. There is great difficulty in keeping carrier mobility high in devices of the deeply submicron generations. A promising avenue toward better carrier mobility is to modify slightly the semiconductor that serves as raw material for device fabrication. It has been known, and recently further studied, that tensilely strained Si has intriguing carrier properties. A Si layer embedded in a Si/SiGe heterostructure grown by UHV-CVD has demonstrated enhanced transport properties, namely carrier mobilities, over bulk Si. In particular, a 90-95% improvement in the electron mobility has been achieved in a strain Si channel n-MOS (Metal Oxide Semiconductor transistor, a name with historic connotations for Si Field- Effect- Transistors (FET)) in comparison to a bulk Si n-MOS mobility. Similarly, a 30-35% improvements in the hole carrier mobility has been obtained for a strained Si channel p-MOS, in comparison to bulk silicon p-MOS. The great difficulty lies in the production of a layer of tensilely strained Si, or SiGe, that are of high enough crystalline quality, namely free of dislocations and other defects, to satisfy the exceedingly elevated demands of microelectronics.
However, if one achieves a material of sufficiently good quality and high carrier mobility, the underlying substrate may be a source of problems in as much as it can be a source of defects that eventually find their way into the good quality material on the surface. An additional potential area of concern may be the interaction of a semiconducting substrate with active devices on the surface. The underlying semiconducting substrate may introduce features which could limit harvesting the full advantage that a superior tensilely strained device layer would bestow. Often today's state of the art devices operate in a semiconducting layer which is separated from the semiconducting substrate by an insulating layer. This technology is commonly knows as SOI technology. (SOI stands for Si-on-insulator.) The standard method of producing SOI materials is called the SIMOX process. It involves the implantation of very high doses of oxygen ions at high energy into the semiconductor, and upon annealing, the oxygen forms an oxide layer under the surface of the semiconductor. In this manner one has a top semiconductor layer separated from the bulk of the substrate. However, the SIMOX process has many of its own problems that makes it unsuitable for the production of high mobility strained layers.
SUMMARY OF THE INVENTION
It is the object of this invention to show a method for producing a high crystalline quality Si based tensilely strained semiconductor layer on a substrate, typically a Si wafer. It is also disclosed how this Si based tensilely strained semiconductor layer can be transferred to another substrate, again most typically to another Si wafer, which is of higher crystalline quality than the substrate on which the strained Si based layer was produced. It is yet a further object of this invention to show how to transfer this Si based tensilely strained semiconductor layer on top of an insulating layer, making the Si based tensilely strained semiconductor suitable for building super-high performance devices.
There are numerous patents and publication relating to this subject. They cover some aspects of strained layer semiconductors, and some aspects of layer transfers and also elements of creating strained layers over insulators. But none teaches the full scope of this invention.
For example, U.S. Pat. No. 5,461,243 to B. A. Ek et al, titled “Substrate for Tensilely Strained Semiconductor” teaches the straining of one layer with another one grown on top of it, and sliding the bottom very thin Si layer on an SiO
2
layer. But this patent does not teach the present invention.
In U.S. Pat. No. 5,906,951 to J. Chu and K. Ismail, titled “Strained Si/SiGe layers on Insulator” incorporated herein by reference, there are a variety layers deposited to yield two strained channels. However this patent again does not teach the present invention.
U.S. patent application “Preparation of Strained Si/SiGe on Insulator by Hydrogen Induced Layer Transfer Technique” by D. Canaperi et al, filed Sep. 29, 2000, Ser. No. 09/675840, (IBM Docket no.: YOR920000345US1) incorporated herein by reference, teaches strain layer deposition and Hydrogen induced layer transfer (SmartCut), but it does not teach the present invention.
Formation of graded SiGe layers can proceed as described in U.S. Pat. No. 5,659,187 to LeGoues et al. titled: “Low Defect Density/arbitrary Lattice Constant Heteroepitaxial Layers” incorporated herein by reference.
The following patent and applications bear reference to both semiconductor strain layer formation and layer transfer. U.S. patent application “A Method of Wafer Smoothing for Bonding Using Chemo-Mechanical Polishing (CMP)” by D. F. Canaperi et al., Serial No. 09/675841 filed Sep. 29, 2000, (IBM Docket No.YOR920000683US1) incorporated herein by reference, describes surface polishing to reduce surface roughness in preparation to wafer bonding. U.S. patent application “Layer Transfer of Low Defect SiGe Using an Etch-back Process” by J. O. Chu, et al, Ser. No. 09/692606 filed Oct. 19, 2000, (IBM Docket No.YOR920000344US1) incorporated herein by reference, describes methods to create relaxed SiGe layers and to use an etch-back process for layer transfer. U.S. Pat. No. 5,963,817 to J. Chu et al, titled “Bulk and Strained Silicon on Insulator Using Local Selective Oxidation” incorporated herein by reference, teaches using local selective oxidation in a layer transfer process.
In all the embodiments of the invention the deposited layers change properties, such as Ge concentration, defect density, dopant concentration, strain state, in the direction of growth, or deposition. In the direction parallel with the surfaces the layers are all uniform. Accordingly, when there is reference that some quantity, for instance Ge concentration, has a variation, this is always meant mean a variation in the thickness direction. The term full thickness refers to the surface, or interface, of a layer where the layer has become fully deposited, or grown.
A typical embodiment of the present invention starts with a standard Si wafer or substrate. In some cases this substrate can have preparatory steps already performed on it for facilitating a layer transfer process to be performed after the layer deposition steps. Such a preparatory step can be, for instance, the creation of a porous layer in connection with the so called ELTRAN (Epitaxial Layer TRANsfer, a registered trademark of Canon K. K.) process. The ELTRAN process is described in U.S. Pat. No. 5,371,037 to T. Yonehara, titled: “Semiconductor Member and Process for Preparing Semiconductor Member”, incorporated here by reference. A step-graded SiGe layer is deposited. The step-grading of Ge concentration substantially proceeds as in U.S. Pat. No. 5,659,187 to LeGoues et al. titled: “Low Defect Density/arb

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