Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-04-28
2003-02-18
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06523157
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to toggle switch information optimization design for designing a high-performance LSI (large scale integrated circuit) through effective use of information on the toggle of circuits in the LSI.
In recent years, very deep sub-micron (VDSM) design has been established for formation of high-density high-integration LSIs by use of the fine semiconductor device formation process. This permits design of more multifunctional and reduced-area LSIs. To assist the VDSM design, technology and systems for accumulating and distributing function components to be placed in an LSI as reusable parts are on the way of establishment.
For example, a design technique is proposed where data for designing a block composed of a plurality of cells for implementing a certain function (for example, one called a function block) is prepared beforehand, and such data is utilized to design a desired system LSI composed of a combination of such blocks. According to this technique, since the structure for implementing the function of each function block has been determined, only design of wiring among function blocks and peripheral circuits is required in the design of the entire semiconductor device. In this way, substantial improvement in design efficiency is intended.
However, as semiconductor elements constituting circuits in the LSI are made smaller and integrated at higher density, there tend to arise problems such as increase in power consumption per unit area and increase in the probability that a local defect in a circuit will adversely affect the entire system, i.e., reduction in reliability. Solving these problems, therefore, becomes important.
In the conventional LSI design, the mainstream of the design is placing importance on the area of LSI that affects the cost and the performance that directly affects the performance. In the VDSM design, in consideration of the above problems, it has become necessary to reorient the stream of the design to place appropriate importance on the power consumption and the reliability in addition to the above aspects.
SUMMARY OF THE INVENTION
In view of the above-noted problems with the prior art technique, an object of the present invention is to provide a device and method for designing an integrated circuit device with high performance in view of power consumption and reliability by optimizing the toggle of circuits in an LSI, which toggle is understood as a factor affecting power consumption and causing a local defect.
The first method for designing an integrated circuit device according to the present invention includes the steps of: (a) generating a plurality of sub-circuits each including a plurality of components placed therein; (b) generating first nets for connecting components placed in a common one of the sub-circuits in the step (a) and second nets for connecting components placed in different ones of the sub-circuits in the step (a); (c) analyzing the toggles of the first nets and the second nets generated in the step (b) by simulating the behaviors of the components; and (d) changing the placement of the components and the connection relationship between the components and the nets based on the analysis results obtained from the step (c) so as to reduce the entire toggle of the first and second nets.
The above method permits circuit design reflecting the difference in power consumption depending on the toggle of the nets, and thus fabrication of an integrated circuit device with reduced power consumption.
In the first designing method, the step (d) includes placing two components connected via one of the second nets of which toggle counts are higher than a value obtained by multiplying an average of the toggle counts of all the nets by a given multiplier in the common sub-circuit. Thus, the placement of the components is modified so that the length of a net having many toggle count is reduced, in consideration that a net extending outside the sub-circuits tends to be long. In this way, design of an integrated circuit device with reduced power consumption as a whole is possible. In addition, the above placement results in reducing the toggle of a long net that tends to be degraded by frequent driving. This minimizes occurrence of local degradation of a specific net.
The second method for designing an integrated circuit device according to the present invention includes the steps of: (a) generating a plurality of sub-circuits each including a plurality of components placed therein; (b) generating first nets for connecting components placed in a common one of the sub-circuits generated in the step (a) and second nets for connecting components placed in different ones of the sub-circuits generated by the step (a); (c) analyzing the toggles of the components in the sub-circuits generated in the step (a) by simulating the behaviors of the components; and (d) changing the placement of the sub-circuits and the components based on the analysis results obtained from the step (c) so as to equalize the toggle counts of all the components.
The above method equalizes the toggle count of the components in the integrated circuit device, and thus minimizes local degradation in the integrated circuit device that may occur when the toggle of a specific component or a specific net connecting components is especially high.
In the second designing method, the step (d) comprises paralleling processing where a sub-circuit out of the plurality of sub-circuits of which toggle counts are equal to or more than a given value is divided into a plurality of parallel sub-circuits. By this processing, degradation in a specific sub-circuit is minimized.
In the second designing method, the paralleling processing is performed so that the increase rate of the area of the integrated circuit device after the paralleling processing does not exceed a given range. This makes it possible to minimize local degradation while minimizing disadvantageous increase in area.
Preferably, the second designing method further includes the step of simulating behaviors of components in the plurality of parallel sub-circuits generated in the step (d) and placing an input control circuit upstream of the plurality of parallel sub-circuits for switching the supply of a signal to the parallel sub-circuits so that the toggle counts of the parallel sub-circuits are equalized.
In addition to the above, more preferably, the second designing method further includes the step of simulating behaviors of components in the plurality of parallel sub-circuits generated in the step (d) and placing an output control circuit downstream of the plurality of parallel sub-circuits for collecting output signals from the parallel sub-circuits to output an output signal.
The third method for designing an integrated circuit device according to the present invention includes the steps of: (a) placing a plurality of components; (b) connecting the components placed in the step (a) via nets; (c) analyzing the toggles of the components placed in the step (a) by simulating the behaviors of the components; and (d) when it is found from the results of the analysis in the step (c) that there exists a component having the same number of input pins as the number of input signals received by the input pins and the input signals can be exchanged between the input pins without changing an output signal although the toggle of the component changes, changing the nets so that the input relationship providing a lower toggle is established.
The above method allows for reduction in the toggle of the components as long as signal transmission is not adversely affected, and thus design of an integrated circuit device with reduced power consumption.
The fourth method for designing an integrated circuit device according to the present invention includes the steps of: (a) placing a plurality of components; (b) connecting the components placed in the step (a) via nets; (c) analyzing the toggles of the components placed in the step (a) by simulating the behaviors of the components; and (d) when it is fo
Motohara Akira
Takahashi Miwaka
Garbowski Leigh M.
McDermott & Will & Emery
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