Method and circuit for processing output data in pipelined...

Details Method and circuit for processing output data in pipelined... Method and circuit for processing output data in pipelined...

2001-03-29

2003-08-12

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

With shift register

C365S219000, C365S221000

Reexamination Certificate

active

06606272

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates in general to integrated circuits that process data in a pipelined fashion, and in particular to an improved data transmission circuit that enhances speed and throughput.
Pipelining techniques have been used in synchronous circuits such as microprocessors and synchronous memories to improve data throughput. There is usually latency associated with pipelined operations. Latency refers to the number of system clock cycles it takes for the first bit of data to propagate to the output of the circuit, after which subsequent bits of data typically arrive within one clock cycle. For example, a synchronous memory circuit such as the synchronous dynamic random access memory (SDRAM), may provide for latency of one, two, three, or higher depending on the system requirements. In the context of SDRAMs, while latency is measured by the number of clock cycles, it is commonly referred to as column access strobe or CAS latency, or CL.
An improved method of pipelining is known as wave pipelining wherein data is serially pipelined to the output, stored in parallel output registers, and then clocked out serially in the sequence received. This type of wave pipelining has been employed in SDRAMs that provide for programmable latency of, e.g., 1, 2 and 3. A common implementation of a wave pipelined SDRAM with a maximum latency of N provides N output data registers (QREG) located near each output terminal (DQ). The N registers store N bits of output data before serially clocking the data out to the output terminal.
FIG. 1
illustrates another implementation of data pipelining wherein a data transmission output circuit
100
utilizes N−1 registers per DQ terminal rather than N registers per DQ terminal. Output circuit
100
includes N−1 output data registers QREG
0
110
, QREG
1
111
, QREG
2
112
, QREG N−1
113
. The input of each register is coupled to an internal data bus
120
. Additionally, the output of each register is coupled to an output terminal DQ
190
. Data is serially provided on the bus
120
and sequentially loaded into each of the N−1 registers in accordance with individual input enable signals EN_QR_IN
0
, EN_QR_IN
1
, EN_QR_IN
2
, and EN_QR_IN_N−1. Data is transmitted from each of the N−1 registers to the output terminal DQ in accordance with individual output enable signals EN_QR_OUT
0
, EN_QR_OUT
1
, EN_QR_OUT
2
, and EN_QR_OUT _N−1. Employing the technique of
FIG. 1
, a CAS latency value L=N may be implemented using only N−1 output registers.
FIG. 2
is a timing diagram illustrating the operation of a data transmission output circuit for the case of a maximum CAS latency of 3 (L=N=3) using N−1=2 registers per DQ terminal. Generally, it is desirable to minimize the clock period and thereby increase the frequency of the system. However, as shown in
FIG. 2
, the minimum clock period for the case of L=3 is constrained by at least two factors. First, the period tAA represents the time between the receipt of the read request and the time the data is available at the output of an output data register (e.g. QREG
0
). Second, the period tRQ represents the time between the receipt of an output enable signal (e.g. EN_QR_OUT
0
) and the time the data signal has propagated to the output terminal DQ and is available for reading. In other words, tAA is the address access time, and tRQ is the propagation time from QREG to output terminal DQ. Accordingly, for L=3, the sum of these two periods must be less than 3 clock cycles. However, tAA is primarily determined by the fabrication process and the inherent delays in accessing and transferring data from the memory array. Furthermore, tRQ is based on the electrical properties of the output circuit (e.g. layout and circuit architecture). Therefore, for L=3, both tAA and tRQ are effectively constant constraints. Therefore, the relation 3*tCLK>tAA÷tRQ must be satisfied. Alternatively, a minimum clock period is given by tCLK, min=(tAA+tRQ)/3. However, for the case of L=3, there is a two clock cycle margin. Therefore, the address access time tAA is typically not a limiting factor for a read request (i.e. two clock cycles plus the time it takes for the first output enable pulse EN_QR_OUT to be removed (tP
2
) is greater than tAA).
One further critical timing constraint on the circuit of
FIG. 1
is that the output enable signal EN_QR_OUT must be disabled before the arrival of the next data bit from the data bus into the output register (e.g. QREG
0
). For example, referring to
FIG. 1
, EN_QR_OUT must be disabled before time marker Ti (i.e. the arrival of Q
2
at QREG
0
). If EN_QR_OUT is not disable before TI, then the new data bit (e.g. Q
2
) will be passed through the output register (e.g. QREG
0
) to the output, and thereby lead to a possible read error. Therefore, the system timing must be constrained such that tP
2
, the point at which the output enable signal is disabled, is less than t
1
, the time between the last prior clock pulse and marker T
1
, the point at which the next data bit arrives from the bus into the output register. Note that t
1
is the access time of data bit Q
2
, and therefore, t
1
=tAA. Accordingly, typical pipelined systems have employed pulsed output enable signals (e.g. EN_QR_OUT<
1
:
0
>) with timing control to serialize the output data such that proper data is transmitted to the output terminal DQ before new data is loaded into the output registers.
However, an N−1 output register implementation of a data transmission output circuit presents a different set of timing requirements when the SDRAM is programmed for a latency less than the maximum latency N (i.e. L<N). Specifically, if the circuit is programmed for L=N−1=2, there is only one clock cycle margin provided for the QREG
0
enable pulse EN_QR_OUT<
0
>.
FIG. 3
is a timing diagram illustrating the operation of a data transmission output circuit for the case of CAS latency of two. Similar to the case of L=N=3 above, there is a timing constraint of 2*tCLK>tAA+tRQ. Accordingly, the minimum clock cycle is tCLK, min=(tAA+tRQ)/2. However, for the case of L=2, the address access time tAA may become a limiting factor. Therefore, in addition to the first constraint, tAA must also not exceed one clock cycle tCLK plus tP
2
. In other words, the data retrieved in response to a read access must be in the output register before the output enable signal is disabled. If tAA is greater than this time period, EN_QR_OUT will be disable before the data arrives in QREG, and the data will not be passed to the output terminal DQ. Thus, in the case of L=2, there is a second limitation that tCLK,min=tAA−tP
2
. Therefore, in the case of L=2 the clock frequency of the system may need to be reduced beyond the minimum defined by tCLK,min=(tAA+tRQ)/2 to ensure that the output enable pulse (i.e. EN_QR_OUT) remains active until after valid data has arrived (i.e., after tAA).
Accordingly, operating a pipelined circuit with a latency value L that is less than the maximum latency N in the N−1 register implementation, results in a speed penalty. What is needed is a circuit and method for processing output data in a pipelined circuit that does not impose timing restrictions that adversely affect the speed of the system.
BRIEF SUMMARY OF THE INVENTION
In accordance with one embodiment of the present invention, a memory circuit includes an output terminal, a plurality of data registers each coupled between the output terminal and a data bus, each storing successive data bits received serially from the data bus, a plurality of enable signals each coupled to a corresponding data register, wherein when one of the plurality of enable signals is active a data bit in the corresponding data register is coupled to the output terminal and when one of the plurality of enable signals is inacti

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