Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-06-11
2003-12-30
Munson, Gene M. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S345000
Reexamination Certificate
active
06670671
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device and its manufacturing method, and more particularly to techniques of realizing high integration and reliability of a nonvolatile semiconductor memory device capable of electrical programming.
Of electrically programmable nonvolatile semiconductor memory devices, a bulk erasable memory or so-called flash memory is known. Flash memories provide excellent portability and shock resistance and are electrically bulk erasable. For these reasons, demands for flash memories as storage devices of compact portable information apparatuses such as portable personal computers and digital still cameras are rapidly increasing. Reduction in a bit cost by a smaller memory cell area is an important factor for market expansion. Various memory cells realizing this have been proposed, for example, as described in “Ohyo Butsuri (or Applied Physics)”, Vol. 65, No. 11, pp. 1114-1124 published by the Japan Society of Applied Physics on Nov. 10, 1996 (hereinafter called “Document 1”).
A virtual ground type memory cell utilizing a three-layer polysilicon gate is described, for example, in JP-B-2694618 (registered on Sep. 12, 1997) corresponding to U.S. Pat. No. 5,095,344. This memory cell is constituted of semiconductor regions formed in a well of a semiconductor substrate and three gates. The three gates include a control gate formed on the well and an erase gate formed between the control gate and a floating gate disposed near each other. These three gates are made of polysilicon and are separated by insulator films. The floating gate and well are also separated by an insulator film. The control gate extending in the row direction constitutes a word line. The source/drain diffusion regions are formed along the column direction and are of a virtual ground type that shares the diffusion regions with adjacent memory cells. With this layout, a pitch in the row direction can be reduced. The erase gate is parallel to the channel and disposed between and in parallel to the word lines (control gates). In writing data in a memory cell described in Document 1, independent positive voltages are applied to the word line and drain, and 0 V is applied to the well, source and erase gate. Hot electrons are therefore generated in the channel region near the drain so that electrons are injected into the floating gate and the threshold voltage of the memory cell rises. In erasing data in the memory cell, a positive voltage is applied to the erase gate, and 0 V is applied to the word line, source, drain and well. Electrons are drained from the floating gate into the erase gate so that the threshold voltage lowers.
A split-gate type memory cell is disclosed, for example, in JP-A-9-321157 (laid open on Dec. 12, 1997). In this memory cell, a large overlap is formed between a diffusion layer and a floating gate to raise the floating gate potential by the diffusion layer potential and apply a low voltage to the word line. In this manner, the efficiency of generating and injecting hot electrons during data write can be improved.
A method of controlling the floating gate potential by the word line and controlling the split channel by a third gate different from the floating and control gates is discussed, for example, in the “Technical Digest” at the International Electron Devices Meeting, 1989, pp. 603-606.
SUMMARY OF THE INVENTION
The channel length is becoming shorter as the flash memory size reduces. A tradeoff between the breakdown voltage between a diffusion layer and a well and punch-through between a source and a drain becomes an important issue, regardless of the type of a memory cell.
The breakdown voltage between the diffusion layer and well is always required to be about 5V or higher during the write operation for the following reason.
For example, in the cell of the type that data is written by hot electron injection, about 12 V is applied to the control gate and about 5 V or higher is applied to the drain to generate channel hot electrons by utilizing a potential difference between the drain and the source applied with 0 V. The breakdown voltage between the drain and source is required to be the drain voltage or higher.
In the cell of the type that data is written by Fowler-Nordheim tunneling electron injection into the whole channel region, for example, about 18 V is applied to the control gate above the floating gate and 0 V is applied to the source/drain to write data by a tunnel current from the inversion layer to the floating gate. In this case, it is necessary to inhibit data write to other cells of the memory array having the same control gate. To this end, for example, about 5 V or higher is applied to the drains of the data write inhibited cells to float the sources so that the inversion channels having the same potential as the drains can be formed under the floating gates. In this manner, the potential difference between the floating gate and well can be reduced and electron tunneling from the channel to the floating gate can be prevented. In this case, the breakdown voltage between the diffusion layer and well is required to be the drain voltage or higher.
In the cell of the type that data is written by electron emission into the diffusion layer, about −12 V is applied to the control gate of a write cell, about 5 V is applied to the diffusion layer, and 0 V is applied to the well to drain electrons in the floating gate into the diffusion layer to write data. In this case, the breakdown voltage between the diffusion layer and well is required to be the drain voltage or higher. For the write inhibited cell having the same control gate as the write cell, 0 V is applied to the diffusion layer to relax the potential difference between the floating gate and diffusion layer.
As above, the breakdown voltage between the diffusion layer and well is required to be about 5 V or higher.
In a flash memory, when data is read, the threshold voltage of a memory cell is checked by generating a potential difference of about 1 V between the source and drain. It is a requisite that this source-drain voltage will not generate punch-through. Other conditions for preventing punch-through must be satisfied depending on the type of a cell.
For example, in the cell of a hot electron injection type, the memory array has cells having the same drain and source as the write cell or has cells having sources and drains respectively being connected by wiring layers. Such a cell is applied with the same drain voltage and source voltage as the write cell. This cell is generally inhibited to write data. If data write throughput is to be improved by parallel programming of a plurality of memory cells within the current drivability of a power source in the chip, it is necessary to prevent leak current between the source and drain of write inhibited cells. It is therefore necessary to prevent punch-through at the source/drain voltage of about 5 V or higher during hot electron injection.
There is another case of a cell called a virtual ground type cell. In the cell of this type, isolation is performed by using a select gate, control gate or the like. As described earlier, in the data write not utilizing injection, a voltage of about 5 V or hither is applied to the diffusion layer. Isolation of the virtual ground type cell from the voltage of about 5 V or higher applied to the diffusion layer is performed by using the control gate or the like. It is therefore necessary to prevent punch-through relative to the diffusion layer.
Low resistance to punch-through between the source and drain to be caused by a short channel has been avoided by implanting ions in the whole channel region and raising the impurity concentration of the channel region. With this method, however, the impurity concentration of a portion of the channel region in contact with the diffusion layer is raised so that the breakdown voltage is lowered.
According to an embodiment of the invention, a nonvolatile semiconductor memory device is provided which has memory cells ea
Kobayashi Takashi
Sasago Yoshitaka
Hitachi , Ltd.
Miles & Stockbridge P.C.
Munson Gene M.
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