Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-07-05
2003-02-04
Ho, Hoai (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
06514848
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the method for forming an interconnection in the semiconductor element.
Increasing attention is paid to Cu which is regarded as the next generation interconnection material in a place of the Al interconnection. The reason for this is that Cu has an excellent electromigration (EM) tolerance as well as small resistance of 1.69 micro ohm cm. However, increase in the current density with downsizing interconnections to microstructure requires the reinforcement of Cu to secure high reliability. One way to make the Cu film highly immune to electromigration is to improve crystalline properties of the Cu film. Therefore, the use of the underlayer texture of TiN film with strong TiN (111) orientation is effective. This is because Cu (111) crystallographic orientation is enhanced on TiN film having strong TiN (111) orientation. (reference document: Extendeded Abstracts of the 1997 International Conference On Solid State Devices and Materials 1997 pp 298-299).
Of late years, the chemical mechanical polishing (CMP) technology introduced for flattening the insulator film begins to be used for forming the Cu interconnections by the Damascene method. Forming an interconnection by the damascene method solves the problem that minute forming of an interconnection by reactive ion etching (RIE) is difficult in case of Cu. In addition, it is advantageous in that the strong coatability of an interlayer film to the step construction is not necessarily indispensable.
However, unlike the formation of an interconnection by the conventional reactive ion etching processing, it is considered that an interconnection formed by the damascene method is influenced by the crystal of the underlying film at the sidewall of the Cu interconnection as well as at the bottom surface thereof. For example, the Cu grain was classified into two. One which faces the sidewalls is classified as the edge region, whereas the other part is classified as the central region. Then, the Cu grain orientation of each region is analyzed. The width of the interconnection of the analytical object is 5 micrometers, and the average grain size of Cu is 0.9 micrometers.
The result of the analysis shows that Cu grains of Cu (111) orientation are decreased in the edge region compared with the central region. This supports the above-mentioned remark. Moreover, it is also well known that narrower width of the interconnection reduces the effect of improvement of a crystalline properties of the Cu film obtained by using said underlying film.
SUMMARY OF THE INVENTION
The object of the present invention has aimed to provide the method for the forming an interconnection in a semiconductor element highly immune to the electromigration by solving the above-mentioned problem, and controlling influence from the underlying film on the minute damascene Cu interconnection in the aspect of crystal.
To achieve the above-mentioned object:
According to the present invention, there is provided a method for forming an interconnection in the semiconductor element, including a process for forming a groove on an underlying substrate so as to correspond to the designed pattern, a process for forming an underlayer to improve crystalline properties of an interconnection which will be formed in the succeeding stage on said underlying substrate with said groove, a process for forming a thin film of the interconnection material, a heat-treatment process to fill the said groove with the thin film of the interconnection material formed on the underlying substrate, and a process for forming the interconnection by polishing the surface of the thin film processed by the heat treatment by predetermined quantity.
In addition, according to the present invention, there is also provided a method for forming an interconnection in the semiconductor element, including a process for forming a groove on an underlying substrate so as to correspond to the designed pattern, a process for forming an underlayer to improve crystalline properties of the interconnection which will be formed in the succeeding stage on said underlying substrate with said groove, a process for forming an underlayer with an insulator film or an underlayer which does not improve the crystalline properties of the interconnection which will be formed in the succeeding stage, a process for forming an underlayer by etching back on the sidewalls of said groove with an insulator film or an underlayer which does not improve the crystalline properties of the interconnection which will be formed in the succeeding stage, a process for forming a thin film of the, interconnection material, a heat-treatment process to fill the said groove with the thin film of the interconnection material formed on the underlying substrate, and a process for forming the interconnection by polishing the surface of the thin film processed by the heat treatment by the predetermined quantity.
Further, according to the present invention, there is also provided a method for forming an interconnection in the semiconductor element, including a process for forming a groove on underlying substrate so as to correspond to the designed pattern, a process for forming an underlayer to improve crystalline properties of the interconnection which will be formed in the succeeding stage on said underlying substrate with said groove, a process in which said underlayer is made amorphous, a process for removing said amorphous underlayer except the same that is formed on the sidewalls of said groove, a process for forming a thin film of the interconnection material, a heat-treatment process to fill the said groove with the thin film of the interconnection material formed on the underlying substrate, and a process for forming the interconnection by polishing the surface of the thin film processed by the heat treatment by the predetermined quantity.
Further, according to the present invention, there is also provided a method for forming an interconnection in the semiconductor element, including a process for forming a groove on an underlying substrate so as to correspond to the designed pattern, a process for forming an underlayer to improve crystalline properties of interconnection which will be formed in the succeeding stage on said underlying substrate with said groove, a process for forming a resist or an insulator film, a process for preserving said resist or said insulator film in the groove by etching back, a process in which said underlayer is removed except the same on the bottom surface of the groove, a process for removing the resist or the insulator film in said groove, a process for forming a thin film of the interconnection material, a heat-treatment process to fill the said groove with the thin film of the interconnection material formed on the underlying substrate, and a process for forming the interconnection by polishing the surface of the thin film processed by the heat treatment by predetermined quantity.
Still, further, according to the present invention, there is also provided a method for forming an interconnection in the semiconductor element, including a process for patterning an underlayer which improves crystalline properties of an interconnection which will be formed in the succeeding stage on an underlying substrate, a process for forming a groove on an underlying substrate so as to correspond to the designed pattern as well as to said underlayer, a process for forming a thin film of the interconnection material, a heat-treatment process to fill the said groove with the thin film of the interconnection material formed on the underlying substrate, and a process for forming the interconnection by polishing the surface of the thin film by the predetermined quantity.
In the above-mentioned method for forming an interconnection in the semiconductor element, at least any one of a multi-layer film of TiN and Ti or a TiN film is used as an underlayer to improve crystalline properties of said interconnection.
In the above-mentioned method for forming an interconnection in the semiconductor
Ho Hoai
Hoang Quoc
Oki Electric Industry Co. Ltd.
Volentine & Francos, PLLC
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