Silicon on insulator self-aligned transistors

Details Silicon on insulator self-aligned transistors Silicon on insulator self-aligned transistors

1995-09-11

2003-11-18

Wille, Douglas A. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S067000

Reexamination Certificate

active

06649977

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to fabricating crystalline silicon microelectronic components, particularly to the fabrication of such components on an insulator (glass) substrate, and more particularly to a self-aligned transistors and a method for fabricating such self-aligned transistors on glass substrates.
Silicon-on-insulator (SOI) technologies have advanced dramatically in recent years towards the goal of producing thin crystalline silicon films on insulator substrates. Components, such as metal-oxide-semiconductors (MOS) transistors, fabricated in SOI films have the potential for increased mobility, reduced parasitic capacitance and leakage current, as well as improved radiation hardness due to reduced junction sidewall area and elimination of bottom junction area. Until recently, there had been no success in achieving crystalline silicon device fabrication on less expensive, low-temperature glass capable of withstanding processing temperature of no more than about 600° C., although such fabrication techniques have been previously achieved using polysilicon on expensive, high temperature glass. SOI transistors on glass substrates are particularly attractive for sensors and flat-panel displays, although many other applications are possible, such as actuators, high temperature electronics, optoelectronics, and radiation hard electronics.
Recently, methods have been developed for achieving single-crystal silicon device fabrication on less expensive glass substrates, wherein the microelectronic components are formed on a silicon substrate, then transferred to a glass substrate, and the silicon substrate is thereafter removed. These recent silicon-on-glass methods are described and claimed in copending U.S. application Ser. No. 08/137,401, filed Oct. 18, 1993, now U.S. Pat. No. 5,395,481 issued Mar. 7, 1998, entitled “A Method For Forming Silicon On A Glass Substrate”; U.S. application Ser. No. 08/137,412, filed Oct. 18, 1993, now U.S. Pat. No. 5,488,012, issued Jan. 30, 1996, entitled “Silicon On Insulator With Active Buried Regions”; U.S. application Ser. No. 08/137,411, filed Oct. 18, 1993, now U.S. Pat. No. 5,399,231 issued Mar. 21, 1995, entitled “Crystalline Silicon Devices On Glass”; and U.S. application Ser. No. 08/137,402, filed Oct. 18, 1994, now U.S. Pat. No. 5,414,276 issued May 9, 1995, entitled “Method For Fabricating Transistors Using Crystalline Silicon Devices On Glass”, each assigned to the same assignee.
These recent efforts have resulted in a significant advance in SOI technologies, as there are significant advantages to utilizing conventional silicon high temperature processing, particularly where there is a need for the capability to produce microelectronic devices on less expensive, low-temperature glasses. These advantages relate to the immediate ability of silicon microelectronics firms to take advantage of this technology without significant capital investment.
While the methods of the above-referenced copending applications Ser. No. 08/137,411 and Ser. No. 08/137,402 have provided a way to utilize the advantages of high temperature silicon processes combined with inexpensive low-temperature glass, these methods require a flat surface for bonding the components to the glass substrate, which limits the range of transistor implementations to non-self-aligned transistors, a slower but still adequate transistor type for most applications. To achieve truly high performance SOI will require self-aligned transistors. The method of the present invention enables the fabrication of self-aligned transistors, with the combined advantages of the above-referenced silicon-on-glass approaches. This is accomplished by providing physical spaces, between the source and the gate, and between the drain and the gate, introduced by etching the polysilicon gate material and providing implanted bridges in the etched regions which allow the transistor to perform normally.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide single-crystal silicon devices on an insulator substrate.
A further object of the invention is to provide a method for forming microelectronic devices on silicon-on-insulator substrates using conventional processing techniques for forming the microelectronic devices, while having the capability of using inexpensive, low-temperature glass as the substrate.
Another object of the invention is to provide silicon on insulator self-aligned transistors.
Another object of the invention is to provide a method for producing self-aligned transistors formed on a silicon substrate and then transferred to a glass substrate.
Another object of the invention is to provide a method for fabricating self-aligned transistors on inexpensive, low-temperature glass, for example, wherein the implanting of the source and drain is carried out at the same time as implantation of the gate.
Other objects and advantages of the invention will become apparent from the following description and accompanying drawing. Basically, the invention involves silicon-on-insulator self-aligned transistors and a method for fabricating same. The invention involves a method generally similar to those of the above-referenced copending applications Ser. No. 08/137,411 and Ser. No. 08/137,402, but basically differs in the simultaneous formation of the gate, drain, and source, whereby self-aligned transistors are produced. In addition, the method of this invention eliminates the use of etch stop layers used in the fabrication methods of the above-referenced application by utilizing an electrochemical etching process to remove the silicon substrate, such as described and claimed in copending U.S. application Ser. No. 08/484,062, filed Jun. 6, 1995, entitled “Silicon On Insulator Using Electrochemical Etching”, and assigned to the same assignee.


REFERENCES:
patent: 3647581 (1972-03-01), Mash
patent: 5086011 (1992-02-01), Shiota
patent: 5206749 (1993-04-01), Zavracky et al.
patent: 5275851 (1994-01-01), Fonash et al.
patent: 5343064 (1994-08-01), Spangler et al.
patent: 5414276 (1995-05-01), McCarthy
patent: 5434441 (1995-07-01), Inoue et al.
E. D. Palik, et al., Ellipsometric Study of the Etch-Stop Mechanism in Heavily Doped Silicon,Journal of Electrochemical Society, vol. 132, No. 1, Jan. 1985, pp. 135-141.
B. Kloeck, et al., Study of Electrochemical Etch-Stop for High-Precision Thickness Control of Silicon Membranes,IEEE Trans. on Electron Devices, vol. 36, No. 4, Apr. 1989, pp. 663-669.
R. Huster, et al., Vertically Structured Silicon Membranes by Electrochemical Etching,Sensors and Actuators, A21-A23 (1990), pp. 899-903.
R. Voss, et al., Light-Controlled, Electrochemical, Anisotropic Etching of Silicon, IEEE, 1991, pp. 140-143.

Affiliated with

Also associated with

Rating

Silicon on insulator self-aligned transistors does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Silicon on insulator self-aligned transistors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Silicon on insulator self-aligned transistors will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3123355