Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2002-05-10
2003-12-02
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S425000, C438S427000, C438S294000, C438S296000
Reexamination Certificate
active
06656816
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to methods for manufacturing a semiconductor device. More specifically, the present invention relates to a method for manufacturing a semiconductor device on which a fine metal oxide semiconductor (MOS) transistor having a shallow trench isolation (STI) structure and a high voltage MOS transistor are mounted in combination.
2. Description of Related Art
Conventionally, formation of a well on a MOS type semiconductor device on which a fine MOS transistor having a local oxidization of silicon (LOCOS) isolation structure and a high voltage MOS transistor are mixed mounted is carried out by using a method shown in
FIGS. 2A through 2E
.
In
FIG. 2A
, the numeral
200
indicates a p-type silcon substrate. A silicon thermal oxide film
201
is formed on the p-type silicon substrate
200
, and a silicon nitride film
202
is formed on the silicon thermal oxide film
201
. Then, a resist
203
is formed on a part of the silicon nitride film
202
corresponding to an isolation area, and the part of the silicon nitride film
202
is pattern-removed using the resist
203
so that a LOCOS oxide film
204
is grown as shown in FIG.
2
B.
After this, as shown in
FIG. 2C
, an ion implantation process is carried out using a photoresist
205
as a mask in order to form a well for a high voltage MOS transistor. Then, as shown in
FIG. 2D
, another ion implantation process is carried out using a photoresist
206
as a mask in order to form a well for a fine MOS transistor. One of the reasons why the ion implantation processes for the wells are performed in two steps is that a relatively low concentration and deep well is required for the high voltage MOS transistor, and a well which is optimized for ensuring excellent MOS transistor characteristics in, for instance, saturation current, punch through, and sub-threshold is required for the fine MOS transistor.
After carrying out the ion implantation processes, a well diffusion process is carried out at high temperature for a long period of time to form a well
207
for the high voltage MOS transistor and a well
208
for the fine MOS transistor as shown in FIG.
2
E. After this, although not shown in the figures, a gate oxide film, a gate electrode, and a source drain diffusion layer are formed to produce the high voltage MOS transistor and the fine MOS transistor, respectively.
Also, a well of a MOS type semiconductor device may be produced by using the following method.
In a fine MOS transistor, since a well which is optimized for ensuring excellent MOS transistor characteristics in, for instance, saturation current, punch through, and sub-threshold is required, a well having a dopant (impurity) concentration distribution in the depth direction (hereinafter referred to as a retrograded well) may sometimes be used. The retrograded well is formed via a plurality of ion implantation processes in which the acceleration energy for implanting ions is optimized.
In the above method, since a thermal treatment at high temperature for a long period of time is not suitable, after an ion implantation process for a well for the high voltage MOS transistor shown in
FIG. 2C
is carried out, a well diffusion process, which is a thermal treatment of high temperature for a long time is carried out to form a well for the high voltage MOS. Then, an ion implantation process for forming a well for the fine MOS transistor is carried out.
Recently, in a fine MOS transistor having improved fineness, the latter method described above as a conventional method is adopted for forming a well in order to obtain excellent MOS transistor characteristics. Also, in the isolation structure, use of the STI is increasing as compared to that of the LOCOS which requires a relatively large isolation width.
In the process of forming a well for the above fine MOS transistor, although a thermal treatment process of high temperature and long period of time is not necessary, it is required to additionally carry out a well diffusion process of high temperature and long period of time in order to form a well for a high voltage MOS transistor. Accordingly, the number of processes is increased and problems may be generated due to the complication in the well formation process.
SUMMARY OF THE INVENTION
The present invention takes into consideration the above-mentioned circumstances, and has an object to provide a method for producing a well which is optimized for a fine MOS transistor and a well which is deep and at a relatively low concentration for a high voltage MOS transistor in a MOS type semiconductor device having a STI structure without increasing the number of manufacturing steps when a fine MOS transistor having excellent MOS transistor characteristics and a high voltage MOS transistor having a high voltage are mounted in combination.
In order to achieve the above objects, the present invention provides a method for manufacturing a semiconductor device, comprising the steps of: forming a first ion implantation expendable film on a first conductive type semiconductor substrate; forming a film for etching mask on the first ion implantation expendable film; patterning the film for etching mask into a shape of an active region and of a field region; forming a mask pattern of a predetermined shape by a photolithography method in accordance with the film for etching mask which has been patterned; introducing a first or second conductive type dopant into the first conductive type semiconductor substrate; forming a trench groove on the first conductive type semiconductor substrate, after removing the mask pattern, by an etching method using the film for etching mask as a mask; forming an insulation film in the trench groove; forming a first well by carrying out an annealing thermal treatment; flattening the insulation film; selectively removing the film for etching mask; removing the whole of the first ion implantation expendable film; forming a second ion implantation expendable film on the first conductive type semiconductor substrate; forming a mask pattern of a predetermined shape by a photolithography method in accordance with the trench groove; and forming a second well by introducing another first or second conductive type dopant into the first conductive type semiconductor substrate.
In accordance with another aspect of the present invention, in the above method for manufacturing a semiconductor device, the first well is a well for a high voltage metal oxide semiconductor (MOS) transistor, and the second well is a well for a fine metal oxide semiconductor transistor.
In yet another aspect of the present invention, the above step for forming the second well by introducing first or second conductive type dopant into the first conductive type semiconductor substrate comprises a plurality of ion introducing steps.
In yet another aspect of the present invention, in the above method for manufacturing a semiconductor device, the temperature of the annealing thermal treatment is in a range between about 1,000 and 1,200° C.
In yet another aspect of the present invention, in the above method for manufacturing a semiconductor device, the step of forming the insulation film in the trench groove comprises a step of forming a first insulation film on inner surfaces of the trench groove and a step of forming a second insulation film for filling the trench groove.
According to the method for manufacturing a semiconductor device described above, after an ion implantation process for a well for a high voltage MOS transistor is carried out prior to the formation of STI, a thermal treatment is performed for repairing crystal defects subsequent to filling an insulation film for the trench groove when the STI is formed so that the well for the high voltage MOS transistor is diffused and the well for the fine MOS transistor is then produced. Accordingly, the thermal treatment process for repairing crystal defects, which is indispensable for the formation of the STI, can be used for the well diffusion process. Hence, since
Anya Igwe W.
Scully Scott Murphy & Presser
Smith Matthew
UMC Japan
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