Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-08-24
2003-11-18
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257S737000
Reexamination Certificate
active
06649506
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating vias in solder pads of a ball grid array (BGA) substrate, and to a method of fabricating electrically conductive vias between the upper circuit layer and the lower circuit layer.
2. Description of the Prior Art
A BGA substrate has been utilized for IC packages for a period of time. Referring to
FIG. 1
, a BGA package comprises a chip
10
, a substrate
20
, an encapsulation
30
, and a plurality of solder balls
40
.
The substrate
20
is a laminated material that was made of an insulating resin. The upper circuit layer
21
and the lower circuit layer
22
formed on the both surfaces of the substrate
20
can be conducted by a plurality of the electrically conductive vias
50
. The chip
10
is combined with the upper surface of the substrate
20
and the circuit layout of the chip
10
is coupled to the upper circuit layer
21
by the golden wires
11
. The surface of the upper circuit layer
21
is covered with a layer of epoxy
23
as a protective layer. On the other hand, in order to prevent the chip
10
and the golden wires
11
from outside effect, the sealed site between the chip
10
and the substrate
20
should be protected by encapsulation
30
.
There is a plurality of solder pads
24
on the surface of the lower circuit layer
22
. The surface of the lower circuit layer
22
is covered with the solder mask
25
, which has a plurality of round holes corresponding to the solder pads
24
. The substrate
20
can electrically contact the printed circuit board (not shown) by a plurality of solder balls
40
soldered with the solder pads
24
.
As described above, the electrically conductive vias
50
serve as the conductors between the upper circuit layer
21
and the lower circuit layer
22
.
The
FIGS.2A
to
2
C illustrate the steps in the process for forming the electrically conductive vias in accordance with the prior art. The steps can be summarized as follows.
(a) Provide an insulating substrate
20
and form a plurality of vias
501
through the substrate
20
by drilling.
(b) Plate the interior surfaces of the vias
501
and the upper surface and the lower surface of the substrate
20
with a thin copper layer
21
a,
22
a,
and then the electrically conductive vias
50
are formed.
(c) Etch the upper thin copper layer
21
a
and the lower thin copper layer
22
a
to form the upper circuit layer
21
and the lower circuit layer
22
.
(d) Plug the epoxy or the conductive resin
502
into the electrically conductive vias
50
.
The above-mentioned prior art has the following defects.
1. The copper layer on the interior surfaces of the electrically conductive vias
50
will be readily microetched or become thinner. Since the plugging step is not performed before the etching step, the copper layer on the interior surfaces of the electrically conductive vias
50
will lack of the protection afforded by the resin. Therefore, it will be readily damaged or become thinner after the etching step, which results in poor reliability.
2. The step (d) of the prior art is to plug the material
502
made of the epoxy or the electrically conductive resin into the electrically conductive vias
50
. The material
502
is not a high solid resin and the plugging step is implemented while the upper surface of the substrate
20
is coated with the epoxy as a protective layer, so the upper surface and the lower surface of the electrically conductive vias
50
plugged with resin are easily sunken, which causes poor reliability.
3. The space used by the electrically conductive vias
50
limits the number of the circuits that can be formed in a given area of a substrate.
SUMMARY OF THE INVENTION
An object of this invention is to provide a method of fabricating vias in solder pads of a BGA substrate. Some high solid content resin is adopted to be plugged into the electrically conductive vias for making the upper surface and lower surface of the both ends of the electrically conductive vias more planar. The sunken problem could be overcome.
Another object of this invention is to provide a method of fabricating vias in solder pads of a BGA substrate. After the both ends of the electrically conductive vias plugged with the resin are roughened by blasting, the both ends of the electrically conductive vias and the upper surface and the lower surface of the substrate are plated with a copper layer. Because the adoption of the roughened method brings the better ability of the adhesion between the resin and the copper layer, the higher reliability could be obtained. The method of fabricating vias in solder pads of a BGA substrate comprises the following steps:
(a) Provide an insulating substrate and form a plurality of vias through the substrate by drilling.
(b) Plate the interior surface of said vias with a thin copper layer by direct plating for forming the electrically conductive vias.
(c) Plug the high solid content of the resin into the electrically conductive vias and remove the redundant resin by scrubbing.
(d) Roughen the surface of said resin by scrubbing and blasting.
(e) Plate the both ends of the electrically conductive vias and the upper and lower surfaces of the substrate with a thin copper layer.
(f) Etch the thin copper layers on the upper surface and the lower surface of the substrate to form the circuit layers, and form the solder pads on the vias.
The above steps are the method of fabricating vias in solder pads of a BGA substrate of this invention. The density of the circuits (dependent upon the diameter of the vias) is about 15~30% more than the prior art. In addition, since the moisture doesn't ventilate from each other, the thin copper layer on the interior surfaces of the electrically conductive vias could be protected and prevented from being damaged by microetching, which results in higher reliability for the BGA substrate.
REFERENCES:
patent: 6010768 (2000-01-01), Yasue et al.
patent: 6376052 (2002-04-01), Asai et al.
Lee Calvin
Phoenix Precision Technology Corporation
Smith Matthew
LandOfFree
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