Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-04-08
2003-06-24
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S324000
Reexamination Certificate
active
06583466
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the manufacture of semi-conductor memory devices and more particularly to a method of manufacture of vertical FET devices formed in trenches in a semiconductor substrate and the devices formed thereby.
2. Description of Related Art
Currently, split gate flash memory devices have a misalignment problem and scaling down issues.
U.S. Pat. No. 5,108,938 of Solomon for “Method of Making a Trench Gate Complimentary Metal Oxide Semiconductor Transistor” shows a FET (Field Effect Transistor) with the source (S) and drain (D) regions on the substrate surface separated by a trench.
U.S. Pat. No. 5,391,506 of Tada et al. for “Manufacturing Method for Semiconductor Devices with Source/Drain Formed in Substrate Projection” shows a method for semiconductor devices with source/drain formed in substrate projection. A projection is formed in a substrate by anisotropic etching and a transistor is contained in the projection. The central portion of the projection covered with a gate electrode is formed as a channel region, and drain and source regions are formed on both sides of the projection by oblique ion implantation with the gate electrode as a mask. However, this reference differs from the configuration of the invention's split gate Flash with the source region at the bottom of the trench and the drain at the substrate surface.
U.S. Pat. No. 5,312,767 of Shimizu et al. for “MOS Type Field Effect Transistor and Manufacturing Method Thereof” shows a vertical SOI (Silicon On Insulator) transistor that has the source S and D regions on opposite ends of a trench. However the device is not a Flash memory.
U.S. Pat. No. 5,229,310 of Sivan “Method of Making a Self-Aligned Vertical Thin-Film Transistor in a Semiconductor Device” shows an EEPROM with a vertical orientation in a trench.
SUMMARY OF THE INVENTION
Objects of this invention are as follows:
1. Scaling down the size of split gate flash memory devices.
2. Providing devices without a misalignment issue for the polysilicon
1
layer and the polysilicon
2
mask.
3. The cell area can be compared with stacked gate flash memory.
A vertical, split gate, flash memory device in accordance with this invention has the features as follows:
1. Small cell area;
2. No misalignment;
3. high channel current.
In accordance with this invention a vertical transistor memory device is provided with FET cells formed in rows and columns with the rows orthogonally arranged relative to the columns. Several cells in a single row have a common source region and adjacent cells have a common drain region. Cells in a single column have separate source regions and separate drain regions. FOX regions are formed between the rows. A set of trenches with sidewalls and a bottom are formed in a semiconductor substrate with threshold implant regions formed in the sidewalls. Doped drain regions are formed near the surface of the substrate and doped source regions are formed in the base of the device below the trenches with oppositely doped channel regions therebetween. A tunnel oxide layer is formed over the substrate including the trenches aside from FOX regions. Floating gates of doped polysilicon are formed over the tunnel oxide layer in the trenches. An interelectrode dielectric layer composed of ONO covers the floating gate layer. Control gate electrodes of doped polysilicon are formed over the interelectrode dielectric layer. Spacers are formed adjacent to control gate electrode sidewalls.
REFERENCES:
patent: 5071782 (1991-12-01), Mori
patent: 5108938 (1992-04-01), Solomon
patent: 5229310 (1993-07-01), Sivan
patent: 5312767 (1994-05-01), Shimizu et al.
patent: 5391506 (1995-02-01), Tada et al.
patent: 5414287 (1995-05-01), Hong
patent: 5705415 (1998-01-01), Orlowski et al.
patent: 5736765 (1998-04-01), Oh et al.
patent: 5841162 (1998-11-01), Enomoto
patent: 0485018 (1992-05-01), None
patent: 408125148 (1996-05-01), None
Chen Shui-Hung
Jung Lin Chrong
Kuo Di-Son
Ackerman Stephen B.
Jones II Graham S.
Pham Hoai
Pham Long
Taiwan Semiconductor Manufacturing Company
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