Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-08-31
2003-12-30
Baderman, Scott (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S710000
Reexamination Certificate
active
06671822
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method and architecture for absorbing defects and improving the yield of a microprocessor having a large on-chip cache. More particularly, the invention relates to improving the yield of a microprocessor having a large on-chip n-way set associative cache by absorbing or working around defects in the portion of the die allocated to cache.
2. Background of the Invention
In general, when designing microprocessor-based systems, system performance can be enhanced by increasing the random access memory (“RAM”) cache available on-chip to the microprocessor. This is because accessing on-chip cache is significantly faster than accessing other off-chip memory, such as single inline memory modules (“SIMMs”) or dual inline memory modules (“DIMMs”). So, at the risk of over-simplifying, the more on-chip cache available the better.
The problem is that increasing available on-chip cache results in increasing the die size for the microprocessor. As the size of the die increases, generally the manufacturing yields for the die decrease. In fact, typically the yield goes down exponentially as the die size is increased. This means that it is harder to manufacture large dies that are not defective.
This creates two competing interests in the design of microprocessors. On the one hand, one would like as much cache as possible available on-chip to increase the speed and efficiency of the microprocessor. On the other hand, any increase in the die size will probably result in reduced production yields for the microprocessor. Industry testing has indicated that for up to about 4 megabytes of cache, the return on speed and efficiency is often worth the resultant manufacturing issues. After that cache size, however, there may be diminishing returns. That is, the benefits of the increased cache size may be outweighed by the reduction in manufacturing yields. Ultimately, a general rule would be that one wants as much cache as can fit on the die while maintaining acceptable production yields.
On typical microprocessor dies, then large areas of the die are allocated to the cache. In fact, the cache typically takes up more physical real estate on the die than anything else. This necessarily means that manufacturing defects in a given microprocessor will often occur in the cache portion of the die since it is the largest physical portion of the die. Accordingly, if there was some way to organize and manage the cache to work around these defects, production yields could be increased. Any method or system that increases the number of defects which a die can absorb while still functioning properly will have a significant yield benefit.
The state of the art currently provides for segmenting the data array of the cache to allow the cache to absorb or “work around” some defects in the data array of the cache. In particular, segmenting the data array of the cache allows for some redundancy and selectivity in the data array that allows the cache to work around some unrepairable defects. For example, by assigning rows and columns to the data array of the cache, row and column redundancy can be used to replace defective rows or columns of the data array. That is, where a particular row or column is found to have an unrepairable defect, it can be replaced with one of the redundant rows or columns that is not defective. Additionally, in a set associative cache where the data array is divided into a plurality of sets or ways, any way found to have a defect can be disabled. This allows an otherwise defective die to still be used, although with a smaller usable cache.
The present invention is directed at a method and architecture for working around defects in a set associative cache, thereby allowing larger on-chip cache while maintaining acceptable manufacturing yields. The present invention can be used in combination with other methods, such as row and column redundancy, to further increase yields.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, there is provided a novel method and architecture for increasing the number of defects in the data array of the cache which can be absorbed while maintaining a useable cache size thereby reducing the percentage of dies which must be discarded due to manufacturing defects. This is accomplished by remapping defective portions of ways in a set associative cache to a surrogate portion of another way in the cache. By utilizing a multiplexer or comparable switching mechanism (“mux”) in the shortest path between the access control logic of the microprocessor and the closest way, additional selectivity can be gained. More specifically, the mux allows smaller portions of the way to be disabled and replaced with a useable portion of a surrogate way, i.e., the way with the shortest path. Since the surrogate way has the shortest physical path, the mux can be added without adding any latency or cycle time. This allows for a larger percentage of die to be repaired, with larger useable cache remaining.
The inventive architecture for set associative cache comprises: a set associative cache having a plurality of ways wherein the ways are segmented into a plurality of banks and wherein a first way has a fast access time; access control logic which manages access to the cache and is coupled to the plurality of ways; a plurality of multiplexers coupled to the first way in each of the banks and coupled to the access control logic; wherein the access control logic controls the multiplexer in a bank to remap any defective way in a bank to the first way in that same bank.
The inventive microprocessor die of the present invention comprises: self test logic which tests the die for defects; a set associative cache having a plurality of ways wherein the ways are segmented into a plurality of banks; access control logic which manages access to the cache coupled to the self test logic and coupled to the plurality of ways in said cache; a first way in the cache which has a physically shorter path to the access control logic; a plurality of multiplexers coupled to the first way in each of the plurality of banks and coupled to the access control logic; wherein the access control logic controls the multiplexer in a bank to remap any defective way in a bank to the first way in that same bank.
The method of absorbing defects in a set associative cache according to the present invention comprises: providing a set associative cache with a plurality of ways wherein the ways are segmented into a plurality of banks and wherein a first way has a fast access time; providing a plurality of multiplexers coupled to the first way in each of said banks; and using the multiplexer in a bank to remap any defective way in a bank to the first way in that same bank.
The computer system incorporating the present invention comprises: an output device to communicate information to a user; a microprocessor comprising: a set associative cache having a plurality of ways wherein the ways are segmented into a plurality of banks; access control logic which manages access to the cache coupled to the plurality of ways in said cache; a first way in the cache which has a physically shorter path to the access control logic; a plurality of multiplexers coupled to the first way in each of the plurality of banks and coupled to the access control logic; wherein the access control logic can control the multiplexer in a bank to remap any defective way in a bank to the first way in that same bank.
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patent:
Asher David H.
Fitzgerald Patrick M.
Grodstein Joel
Lilly Brian
Baderman Scott
Hewlett--Packard Development Company, L.P.
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