Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1999-09-03
2003-02-25
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S114000, C710S052000
Reexamination Certificate
active
06526477
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to RAID systems, and more particularly to RAID systems that provide RAID functions by utilizing the memory of a host computer system.
2. Description of the Related Art
Since the inception of computers, data protection has been one of the main concerns in designing data storage systems. Valuable data stored in hard drives can be lost due to abnormal occurrences such as human errors, equipment failures, and adverse environmental conditions. With the advent of on-line, interactive computing, the protection of data has become an even more important consideration in designing data storage systems. For example, modern e-commerce enables companies to conduct all or sizable portion of their business over the Internet using computers. In such scenario, if hard drives on a company's server computer fail, the company's business may come to a standstill. This may lead to a substantial loss in business and goodwill to its customers.
To guard against such disastrous events and enhance I/O performance, many computer systems implement a Redundant Array of Independent Disk (RAID) system, which is a disk system that includes a collection of multiple disk drives and an array controller. The disk drives are organized into a disk array and managed by the common array controller. The array controller presents the array to the user as one or more virtual disks. Disk arrays are the framework to which RAID functionality is added in functional levels to produce cost-effective, highly available, high-performance disk systems.
In RAID systems, data is distributed over multiple disk drives to allow parallel operation, thereby enhancing disk access performance and providing fault tolerance against drive failures. Currently, a variety of RAID levels (e.g., RAID level 0 through level 6) has been specified in the industry. For example, RAID level 5 architecture provides enhanced performance by striping data blocks among N disks and provides fault-tolerance by using 1/N of its storage for parity blocks, which are typically calculated by taking the exclusive-or (XOR) results of all data blocks in the parity disks row. The I/O bottleneck is thus reduced because read and write operations are distributed across multiple disks. RAID systems are well known in the art and are amply described, for example, in
The RAID Book, A storage System Technology Handbook
, by Paul Massiglia, 6th Ed. (1997), which is incorporated herein by reference.
FIG. 1A
illustrates a schematic block diagram of a conventional computer system
100
having a dedicated-memory RAID system. The computer system
100
includes a host processor
102
, a primary PCI bus
104
, a host memory
106
, a host adapter card
120
, and a RAID array
112
. The host processor
102
is coupled to the PCI bus
104
for processing information such as data and instructions. The memory
106
is also coupled to the bus
104
for storing and providing information for the processor
106
.
The primary PCI bus
122
is commonly known as a host bus, to which peripheral devices can be connected to provide additional functionality. For example, as shown in
FIG. 1
, the RAID array
112
, which is comprised of a plurality of disk drives
118
, is coupled to the PCI bus
122
through the host adapter card
120
. The host adapter card
120
is configured to interface and control access to the RAID array
112
and includes a PCI-PCI bridge
108
, a secondary PCI bus
122
, a PCI-SCSI controller
110
, a RAID accelerator
114
, and a dedicated memory
116
.
In the host adapter card
120
, the PCI-PCI bridge
108
is coupled to the PCI-SCSI controller
110
and the RAID accelerator
114
via the secondary PCI bus
122
. The PCI-PCI bridge
108
is a well known device that is used to connect the primary PCI bus
104
with the secondary PCI bus
122
for transmitting from one bus to the other. The PCI-SCSI controller
110
is coupled to interface with the disk array
124
through a peripheral SCSI bus
124
and controls access to the individual disk drives
118
.
The RAID accelerator
114
is coupled to the dedicated memory
116
and accesses the dedicated memory to facilitate generation of parity data for storage in the disk array
124
. In addition, the RAID accelerator
114
uses the dedicated memory for performing error correction coding (ECC) including encoding and decoding for error detection and correction. As can be appreciated, the RAID accelerator
114
includes a memory controller (not shown) for controlling the access to the dedicated memory
116
. The PCI-SCSI controller and RAID accelerator may be implemented using chips such as AIC7880™ and AIC7815™, respectively, which are available from Adaptec, Inc. of Milpitas, Calif.
FIG. 1B
illustrates a conventional method for generating parity data in the RAID system for a RAID 5 partial stripe write operation using the dedicated memory
116
. As is well known, in a RAID 5 partial stripe write operation, data is stored as data chunks in data stripes the RAID array
112
and one or more data chunks in a data stripe are modified. By comparison, a full stripe write operation entails accessing all data chunks in a stripe and generating new parity data for the entire stripe before writing to the RAID array
112
.
With reference to
FIG. 1B
, the method begins in operation
152
and proceeds to operation
154
, where the RAID accelerator
114
receives new data from a buffer in the host memory
106
and stores the new data in the dedicated memory
116
. Then, in operation
156
, the new data is copied into an XOR buffer space in the dedicated memory
116
. Next, old data and old parity data, which are existing data on the disk array
112
, are accessed from the disk array
112
, and copied into the XOR buffer space in the dedicated memory
116
in operation
158
. Once the new data, old data, and old parity data have been loaded into the dedicated memory
116
, the RAID accelerator
114
accesses the stored data, in operation
160
, to perform XOR operation to generate new parity data. The new data and new parity data are then stored into the disk array
112
in operation
162
. The method then terminates in operation
164
.
Unfortunately, the use of RAID accelerator
114
having its own dedicated memory
116
is costly to implement. For example, the dedicated memory
116
typically requires substantial amount of memory (e.g., eight Megabytes) to implement XOR function. In addition, the use of the dedicated memory
116
requires a memory controller, typically incorporated in the RAID accelerator chip, to control access to the memory
116
. Furthermore, the ECC function requires complex circuitry to implement in the RAID accelerator
114
. These additional functions thereby drive up the cost of the host adapter card significantly.
In addition, the PCI-PCI bridge
108
typically includes a small buffer for buffering data transmitted from one bus to the other. However, the buffer often causes a bottleneck in communication between the host PCI bus
104
and the secondary PCI bus
122
. Hence, the PCI-PCI bridge
108
may often limit the performance of the computer system.
One of the most popular buses is the well known small computer systems interface (SCSI) bus, which is defined in conformity with SCSI protocols (e.g., SCSI-1, SCSI-2, SCSI-3, etc.), which are incorporated herein by reference. The SCSI protocols are designed to provide an efficient peer-to-peer I/O interface between a host computer system and its peripheral devices. A SCSI bus may accommodate a plurality of SCSI devices up to a number equal to the number of data bits in the SCSI bus. For example, the SCSI-2 bus may accommodate up to eight devices, of which one is usually a SCSI host adapter.
Thus, what is needed is a system and method for providing RAID functions in a host adapter card without the high cost and performance limitations of the conventional techniques.
SUMMARY OF THE INVENTION
The present invention fills these needs by providing a low-cost host-memory base
Lie Jimmy S.
Yuan Joe J.
Adaptec, Inc.
Martine & Penilla LLP
Namazi Mehdi
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