Modular bus with single or double parallel termination

Details Modular bus with single or double parallel termination Modular bus with single or double parallel termination

1996-07-12

1997-09-02

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

327292, H03K 1716, H03K 19003

Patent

active

056636610

ABSTRACT:
A modular bus permitting single or double termination is described. The bus includes a terminated motherboard data net for communicating data signals between a master and one or more motherboard devices. A socket is used for coupling the data signals between the motherboard data net and a terminated module data net of a removable module. The module data net communicates the data signals between the master and one or more module devices. The data signal swing and level of reflection of the data signals are substantially independent of the presence of the module.

REFERENCES:
patent: 4987318 (1991-01-01), Burke et al.
patent: 5003467 (1991-03-01), Donaldson et al.
patent: 5046072 (1991-09-01), Shimizu et al.
patent: 5434516 (1995-07-01), Kosco
"Adaptive Control of Off-Chip Drivers", IBM Technical Disclosure Bulletin, vol. 33, No. 7, Dec. 1990, pp. 267-268.
Taguchi, Masao, "High-Speed, Small-Amplitude I / O Interface Circuits for Memory Bus Application", IEICE Transactions on Electronics, vol. E77-C, No. 12, Dec. 1994, pp. 1944 -1950.
Patent Abstracts of Japan, vol. 14, No. 483 (E-0993), 22 Oct. 1990, p. 1 of 1. (JP2198226, Jun. 8, 1990, Atsushi).

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