Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-08-15
2003-12-30
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06671857
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to design technology for integrated circuit devices such as system LSI, and more particularly, relates to smoothing designing in a sequence of design process steps up to register-transfer level (RTL) design process step.
In general, design of an integrated circuit device is performed in a procedure as shown in
FIG. 42
, where specification/behavioral level design (S
91
) comes first followed by RTL design (S
92
), gate level design (S
93
), and mask level design (S
94
) in this order.
In the specification/behavioral level design, specifications and behavior for implementing a certain function are designed. In the RTL design, data throughput and the time required for processing data, as well as hardware configuration and the area occupied by the hardware, are taken into consideration.
The subsequent designs lower in level than the RTL design have been automated, and therefore design data can be generated without the necessity of manual work.
On the contrary, the upper-level designs including the RTL design have been little automated. Design and optimization are performed by skilled designers. Local optimization is therefore difficult due to restriction on the number of steps and the like, and thus only broad-perspective optimization has been made. If local optimization can be done in the upper-level designs, a great effect may possibly be exerted on the entire design. In consideration of this, a simple and convenient optimization design method has been desired.
Conventionally, there has been established no standard information style exchangeable between the specification/behavioral level design and the RTL design. Accordingly, it is impossible to correctly grasp information on the RTL design at the stage of the specification/behavioral level design. For this reason, even a skilled designer tends to prepare, at the stage of the specification/behavioral level design, a design unable to be implemented in the RTL design. As a result, it may become necessary to correct the specification/behavioral level design after completion of the RTL design. Otherwise, a redundant circuit may be designed at the specification/behavioral level.
SUMMARY OF THE INVENTION
An object of the present invention is providing a method and an apparatus for designing an integrated circuit device, capable of designing a large-scale system such as system LCI efficiently by use of common information of the number of operations that is shared in the specification/behavioral level design process step and the RTL design process step, and capable of performing simple and convenient optimization design in these design process steps.
The first method for designing an integrated circuit device of the present invention is a method including representing a portion constituting the integrated circuit device by a three-dimensional shape, the type of the three-dimensional shape being determined depending on a design level.
By the above method, the structure of an element or a bus that is sequentially concretized in the course of specification level—behavioral level—RTL can be represented by three-dimensional shapes that allow for prompt grasp of the structure. This contributes to improvement in design efficiency. More specifically, since it is possible to roughly grasp the structure of an element or a bus in high-level design that is required for design of an integrated circuit device, the structure of a design model can be easily limited to an appropriate range. This reduces the possibility of such an occurrence that high-level design must be done again as a result of low-level design.
When the integrated circuit device has a plurality of functions, the above portion comprises a plurality of elements required for implementing the plurality of functions, and each of the plurality of elements may be represented by a three-dimensional shape of which a volume corresponds to the number of operations required for implementing the function.
In design at a level lower than a specification level, the element may be represented by a pole of which a bottom area corresponds to the number of operations per cycle.
In behavioral level design, the element may be represented by a cylinder of which a bottom is a circle having an area corresponding to the number of operations per cycle.
In RTL design, the element may be represented by a square pole of which a bottom has two adjacent sides corresponding to the number of operations per unit time and the period of a cycle.
When the portion comprises a bus connecting the plurality of elements, a connection relationship between the bus and each of the elements may be represented by a three-dimensional shape so that a structure of the bus and a structure of the element match each other using the number of operations per unit time as a medium.
In design at a level lower than a specification level, the element may be represented by a pole of which a bottom area corresponds to the number of operations per cycle, and the bus may be represented by a pole of which a bottom area corresponds to the number of operations per cycle.
Preferably, in behavioral level design, the element is represented by a cylinder of which a bottom is a circle having an area corresponding to the number of operations per cycle, and the bus is represented by a cylinder of which a bottom is a circle having an area corresponding to the number of operations per cycle.
Preferably, in RTL design, the element is represented by a square pole of which a bottom has two adjacent sides corresponding to the number of operations per unit time and a period of a cycle, and the bus is represented by a square pole of which a bottom has two adjacent sides corresponding to the number of operations per unit time and a period of a cycle.
When the bottom areas of the bus and the element are different from each other, the bus may be represented by a cone of which two faces correspond to the bottoms of the bus and the element.
A bus branch branching from the bus to be connected to the element may further be generated, the bus branch being represented by a pole having a cross-sectional area equal to the bottom area of the bus.
The second method for designing an integrated circuit device of the present invention includes the steps of: (a) obtaining the number of operations by simulating a function of the integrated circuit device; (b) determining specification level elements so that each of the elements has the number of operations equal to or more than the number of operations obtained in the step (a); (c) determining a bus connecting the elements; (d) determining behavioral level elements so that each of the elements has the number of operations per cycle and the number of cycles that give the number of operations equal to or more than the number of operations determined in the step (b); and (e) determining a behavioral level bus for connecting the behavioral level elements based on the number of operations per cycle determined in the step (d).
By the above method, consistent design based on the number of operations of an element and a bus is possible through the respective design stages.
In the step (b), if a plurality of practicable specification level elements exist, one among the elements that has the least number of operations may be determined as the specification level element used for design. With this determination, a circuit small in circuit area and power consumption can be obtained.
In the step (d), in the case where a plurality of practicable behavioral level elements exist, if design is made giving higher priority to operation speed, an element among the behavioral level elements that has the number of operations per cycle as large as possible may be determined as the behavioral level elements used for design, or if design is made giving higher priority to a smaller circuit area or smaller power consumption, an element among the behavioral level elements that has the number of operations per cycle as small as possible may be determined as the behavioral level element used for des
Motohara Akira
Ohashi Masahiro
Takahashi Miwaka
Yokoyama Toshiyuki
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Thompson A. M.
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