Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-09-29
2003-12-09
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S121000, C711S133000
Reexamination Certificate
active
06662272
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
Not Applicable.
STATEMENTS REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
REFERENCE TO A MICROFICHE APPENDIX
Not Applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to cache organization and more particularly to dynamic cache partitioning.
2. Description of the Related Art
In a computer system, a cache is the first level of memory hierarchy encountered once an address leaves a processor toward a memory subsystem. A cache uses the principle of locality to buffer commonly used addresses. Caches improve system performance by reducing memory access latencies and by reducing bandwidth consumption on a processor front side bus. A cache operates on a processor backside bus with processors such as Intel's Pentium III Xeon processor. Many of today's processors include integrated level-one (L1) and level-two (L2) caches. Computer systems can employ a cache external to the processor in addition to these internal caches.
Modern operating systems can issue multiple threads and processes that may share a cache. When a thread or process is pre-empted, the new thread or process could replace the cache contents of the previous thread or process. When the original thread or process returns, its memory ranges may no longer be cached. The original thread or process may then cache its memory ranges and replace what was cached by the previous thread or process. This behavior is termed “thrashing” a cache. Operating systems and more generally the overall software model of computer systems can significantly contribute to cache thrashing.
Multi-processor computer systems in which multiple processors share a cache also greatly contribute to cache thrashing. For instance, a context switch may occur that shifts to a process for a processor after a previous process for a different processor was cached. Similarly, when logical processors become available from a single physical processor package, threads or processes for one logical processor will likely pre-empt previous threads or processes of another logical processor and replace the cache contents of these previous threads or processes.
Increasing the associativity of caches, optimizing process or thread scheduling and optimizing memory management are common strategies employed in an effort to address cache thrashing.
BRIEF SUMMARY OF THE INVENTION
Briefly, a cache-based system is adapted for dynamic cache partitioning. A cache is partitioned into a plurality of cache partitions for a plurality of entities. Each cache partition can be assigned as a private cache for a different entity. If a first cache partition satisfying a first predetermined cache partition condition and a second cache partition satisfying a second predetermined cache partition condition are detected, then the size of the first cache partition is increased by a predetermined segment and the size of the second cache partition is decreased by the predetermined segment. An entity can perform cacheline replacement exclusively in its assigned cache partition, and also be capable of reading any cache partition.
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Guohua Jin et al.,An Efficient Solution to the Cache Thrashing Problem, pp. 1-26 (Mar. 4, 1996).
Jenne John E.
Jones Phillip M.
Olarig Sompong P.
Hewlett--Packard Development Company, L.P.
Nguyen Hiep T.
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