Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-04-11
2003-02-11
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06519757
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the design of very large scale integrated circuits. Particularly, it relates to providing data descriptive of functional specifications for instantiating circuit descriptors for hardware design programs. More particularly, it relates to the design of a new level of hierarchy for communication between an integrated circuit and its external environment.
2. Description of the Related Art
Design of VLSI (very large scale integrated) circuits typically employs a substantial number of input and output library elements. Each element typically requires two to five, sometimes more, connections for coupling signals to circuits internal to a integrated circuit chip. These include data and control signals. A VLSI circuit with 500 input/output pins may require as many as 2500 connections to connect each library book (circuit element).
Hardware design language for implementing integrated circuits requires extensive lines of code. The complications of VLSI exacerbates the problems of specifying and maintaining input to the software. One of the industry standard languages, VHDL (Very High Speed Integrated Circuit Hardware Design Language), requires a component instantiation for each of the 500 library books (technology-specific library entries, e.g., an AND gate). Such instantiations are usually entered at the top design level which tends to obfuscate the functional elements and complicates the maintenance of the design. This requires several new constructs which have to be created and maintained. Furthermore, it is sometimes desirable or necessary to comport with IEEE 1149.1 JTAG (Joint Action Test Group) connections.
BRIEF SUMMARY OF THE INVENTION
The invention provides a capability of correctly constructing the entity, every driver, every receiver, every bidirectional device, and their interconnections by creating a level of hierarchy for the input/output connections to integrated circuits. The invention is a process which transforms the language of a functional specification to generate replacement for manual entry of many thousands of lines of code, it provides the further capability of permitting changes, e.g., from a unidirectional port to bidirectional port, simply and quickly without the necessity of replacing numerous lines of code.
It simplifies the task of generating every construct necessary to automate fully the input/output inclusion in a design and eliminating the manual steps required in the prior art. An implementation of the invention generates the code for declaring component designations for each new design, defining a integrated circuit chip entity and component definition, the input/output definitions of entities, architectures, and components, signal definition for inclusion in a integrated circuit chip architecture, detection, exploding, and imploding bus design as necessary, JTAG inclusion, and connections for high impedance control during reset.
In accordance with the invention, a hardware design program converts functional specifications to hardware implementations according to functional specifications. Descriptive language statements representative of a desired hardware implementation are supplied, and descriptive language statements are transformed into functional language for input to the hardware design program. The descriptive language statements define a separate communication hierarchy level positioned between the functional hardware logic and the external environment.
REFERENCES:
patent: 5146583 (1992-09-01), Matsunaka et al.
patent: 5432708 (1995-07-01), Mohsen
patent: 5493507 (1996-02-01), Shinde et al.
patent: 5537580 (1996-07-01), Giomi et al.
patent: 5541849 (1996-07-01), Rostoker et al.
patent: 5544067 (1996-08-01), Rostoker et al.
patent: 5696771 (1997-12-01), Beausang et al.
patent: 5751592 (1998-05-01), Takai et al.
patent: 5761484 (1998-06-01), Agarwal et al.
patent: 5841663 (1998-11-01), Sharma et al.
patent: 5848263 (1998-12-01), Oshikiri
patent: 5862361 (1999-01-01), Jain
patent: 5867399 (1999-02-01), Rostoker et al.
patent: 5870308 (1999-02-01), Dangelo et al.
patent: 5892682 (1999-04-01), Hasley et al.
patent: 5903475 (1999-05-01), Gupte et al.
patent: 6021266 (2000-02-01), Kay
patent: 6058492 (2000-05-01), Sample et al.
patent: 6152612 (2000-11-01), Liao et al.
patent: 6265995 (2001-07-01), Sahejpal et al.
patent: 6321366 (2001-11-01), Tseng et al.
patent: 6363520 (2002-03-01), Boubezari et al.
patent: 6401230 (2002-06-01), Ahanessians et al.
patent: 6421808 (2002-07-01), McGeer et al.
patent: 6438739 (2002-08-01), Yamada
Lima et al. (“Logic and high level synthesis for communication protocols”, Proceedings of XII Symposium on Integrated Circuits and Systems Design, Sep. 29, 1999, pp. 142-145).*
Hwang et al. (“On the control-subroutine implementation of subprogram synthesis”, Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, Jan. 28, 1997, pp. 587-592).*
Ecker et al. (“VHDL-based communication- and synchronization synthesis”, Proceedings EURO-DAC '95, European Design Automation Conference, with EURO-VHDL, Sep. 18, 1995, pp. 458-462).*
Huang et al. (“ICEBERG: an embedded in-circuit emulator synthesizer for microcontrollers”, Proceedings of 36th Design Automation Conference, Jun. 21, 1999, pp. 580-585).
Bullis Bryan Keith
Gerowitz Robert Glen
Kik Phallaka
Smith Matthew
Wright Carl M.
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