Systems and methods for on-chip impedance termination

Details Systems and methods for on-chip impedance termination Systems and methods for on-chip impedance termination

2002-01-11

2003-08-05

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S083000, C326S086000, C327S108000, C327S404000, C327S308000

Reexamination Certificate

active

06603329

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to techniques for on-chip impedance termination, and more particularly, to on-chip impedance termination at differential input/output pins that saves board space.
Prior art integrated circuits have included a high speed input/output (I/O) standard known as the low voltage differential signal (LVDS) standard. The LVDS standard refers to a method for inputting and outputting differential signals across I/O pins of an integrated circuit. A differential input signal is typically applied across two LVDS pins of an integrated circuit and to a buffer circuit that drives the input signal to circuitry within the integrated circuit. The LVDS standard is well-known in the art.
An input voltage signal applied to differential LVDS I/O pins varies by a AC (alternating current) value. The buffer circuit outputs a voltage signal indicative of a logic HIGH or a logic LOW in response to the voltage of the input signal across the LVDS I/O pins.
An external resistor is coupled between each pair of LVDS pins off-chip to provide impedance termination and voltage swing for the differential input signals applied to the LVDS pins. The impedance termination resistor reduces reflection of input signals on differential signal lines coupled to the LVDS pins. Coupling an external resistor to each pair of LVDS pins on an integrated circuit may use a substantial amount of board space. Therefore, it would be desirable to provide a technique for providing impedance termination for differential I/O pins in an integrated circuit that does not occupy as much board space.
BRIEF SUMMARY OF THE INVENTION
Techniques for on-chip impedance termination are provided that substantially reduce the number of external resistors that are needed to provide impedance termination at a plurality of pairs of differential input/output (I/O) pins. On-chip impedance termination circuits of the present invention may include an amplifier, a feedback loop, and an impedance termination circuit. A reference voltage is provided to a first input terminal of the amplifier. A feedback loop is coupled between an output terminal of the amplifier and a second input terminal of the amplifier. The amplifier drives its output voltage so that the voltage at the second input terminal matches the voltage at the first input terminal.
The output voltage of the amplifier determines the resistance of the impedance termination circuit. The impedance termination circuit is coupled between differential I/O pins. The amplifier may be coupled to impedance termination circuits for numerous pairs of differential I/O pins on an integrated circuit.


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