Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral configuration
Reexamination Certificate
2002-01-04
2003-02-11
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral configuration
C710S008000, C710S062000, C710S072000, C710S074000, C710S301000, C711S105000, C711S170000
Reexamination Certificate
active
06519658
ABSTRACT:
TECHNICAL FIELD
The invention relates to memory systems. The invention also relates to fiber optic systems.
BACKGROUND OF THE INVENTION
Processor speeds of computers continue to increase. Devices with which the processor communicates often do not operate at such high speeds. For example, static random access memories (SRAMs) often operate at almost as high a speed as the processor, but dynamic random access memories (DRAMs) operate at a slower speed. Dynamic random access memories possess advantages to static random access memories. For example, static random access memories require more space than dynamic random access memories.
Rambus Inc. of Mountain View, Calif. has technology that allows DRAMs and controllers or processors to transfer data at a high frequency, such as 600 megabytes per second and above over a Rambus Channel, a narrow byte-wide data bus. Attention is directed to the following patents assigned to Rambus, Inc., which are incorporated herein by reference: U.S. Pat. No. 5,680,361 to Ware et al.; U.S. Pat. No. 5,663,661 to Dillon et al.; U.S. Pat. No. 5,537,573 to Ware et al.; U.S. Pat. No. 5,499,385 to Farmwald et al.; U.S. Pat. No. 5,499,355 to Krishnamohan et al.; U.S. Pat. No. 5,485,490 to Leung et al.; U.S. Pat. No. 5,446,696 to Ware et al.; U.S. Pat. No. 5,432,823 to Gasbarro et al.; U.S. Pat. No. 5,430,676 to Ware et al.; U.S. Pat. No. 5,390,308 to Ware et al.; U.S. U.S. Pat. No. 5,355,391 to Horowitz et al.
An alternative to Rambus has been developed by memory chip makers. The synchronous link DRAM (SLDRAM) is an alternative to double-data-rate (DDR) and Direct Rambus DRAM.
The SLDRAM is known in the art. The SLDRAM, formerly known as SynchLink, is designed for computer main memory in mobile, desktop, workstation, and server systems. It is designed to reduce a speed bottleneck in accessing memory from a processor. The SLDRAM project attempts to solve a memory system problem that will become more acute in newer systems. DRAM memory chips do not have enough bandwidth for getting the data on or off the memory chips. To solve this problem, manufacturers have been using many chips in a wide array to get the speed up to what their system needs. However, new DRAM chips will have increasingly higher capacities, so that there will be so much DRAM capacity in the wide array of chips needed forgetting the speed, that the price of the DRAM capacity raises the price of the computer. For lower price or entry-level computers and workstations, this price may be excessive. Unnecessarily large memory would exist in base configurations. Although new software uses more memory, that memory usage is not growing as fast as DRAM density, and this mismatch may result in overly expensive computers.
SLDRAM addresses this problem by using a new architecture for communicating with the DRAMs, with two highly optimized buses. This allows increasing the DRAM bandwidth significantly. SLDRAM adds pipelined transfer protocol for increased advantage of bandwidth. Attention is directed to the SLDRAM White Paper of Aug. 29, 1997, which describes SLDRAM in greater detail.
SLDRAMs are synchronously linked to processors. To provide high speed access to the memories, as processor speed increases, lengths of circuit traces should decrease.
It is known to use optical wave guides as interconnects from integrated circuit to integrated circuit. See, for example, U.S. Pat. No. 5,119,451, which is incorporated herein by reference. Various R&D efforts have taken place in an attempt to develop optical interconnect technology for short-haul data communications applications such as for communications between boards, backplanes, and intra-boxes. See, for example, “Lighting the Way in Computer Design,” IEEE Circuits & Devices, January 1998.
SUMMARY OF THE INVENTION
The invention provides a computer. The computer includes a housing, and a circuit board supported in the housing. A plurality of slot connectors are supported on the circuit board. A first card is configured for sliding receipt in one of the slot connectors. A processor is mounted on the first card. A second card is configured for sliding receipt in one of the slot connectors. A memory is mounted on the second card. An optical interconnect couples the first card to the second card. The processor is configured to communicate with the memory via the optical interconnect.
In one aspect of the invention, the optical interconnect comprises a fiber optic cable.
In another aspect of the invention, the optical interconnect comprises an optical connector on the first card configured to convert between electrical signals and optical signals, and the computer further includes circuit traces on the first card coupling the optical connector to the processor.
In another aspect of the invention, the optical interconnect comprises an optical connector on the second card configured to convert between electrical signals and optical signals, and the computer further includes circuit traces on the second card coupling the optical connector to the memory.
In another aspect of the invention, the memory comprises a DRAM. In another aspect of the invention, the memory comprises a synchronous link type DRAM.
Another aspect of the invention provides a memory unit configured to be slidably received in a slot connector on a circuit board. The memory unit comprises a card having a connector configured to mate with the slot connector. A synchronous link DRAM memory is supported by the card. Circuit traces on the card extend from the connector of the card toward the memory. The circuit traces are configured to couple the memory to a power supply via the slot connector. An optical interface is supported by the card and coupled to the memory. The optical interface is configured to convert electrical signal to optical signals, for optical data transmission to and from the memory.
Another aspect of the invention provides a method of assembling a computer. The method comprises supporting a circuit board in a housing. A plurality of slot connectors are supported on the circuit board. A processor is mounted on a first card. The first card is inserted into a first one of the slot connectors. A memory is mounted on a second card. The second card is inserted into a second one of the slot connectors. The first card is optically connected to the second card for optical communications between the processor and the memory.
By reducing the circuit trace path on a memory card, communication speed is increased. Inexpensive circuit cards can be used instead of Teflon substrate or low dielectric cards. Memory integrated circuits can be mounted on cards prior to burn-in because the circuit cards are inexpensive. This is less expensive than burning-in memory integrated circuits before they are mounted on circuit cards. Unsophisticated users can add memory and integrated circuits easily. They can insert a SIMM module or card, attach one end of the fiber optic cable to an optical interconnect on the SIMM module, and attach the other end of the fiber optic cable to the optical interface on the processor card, and the installation is complete. Electromagnetic interference caused by power supply transformers or disk drives is less of a concern because the optical communications are immune to such interference.
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Farnworth Warren M.
Wood Alan G.
Gaffin Jeffrey
Micro)n Technology, Inc.
Perveen Rehana
Wells St. John P.S.
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