Power-supply-configurable outputs

Details Power-supply-configurable outputs Power-supply-configurable outputs

2000-12-01

2003-06-10

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C326S038000, C326S062000, C326S080000, C326S081000, C326S086000, C327S112000, C327S178000, C327S530000, C365S051000, C365S189090, C365S205000, C365S230030

Reexamination Certificate

active

06578185

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to noise suppression generally and, more particularly, to power-supply configurable outputs for decreasing noise excursions on internal power busses for output drivers.
BACKGROUND OF THE INVENTION
Switching output transistors at high speeds. can introduce noise on the output power supply nodes of an integrated circuit. Switching high currents can also introduce noise. Noise excursions on the internal output supply nodes degrade the performance of MOS output transistors during high speed and high current conditions.
One conventional method of reducing noise on the internal output supply nodes is to increase the number of dedicated supply pins. However, increasing the number of dedicated supply pins decreases the number of available data and control pins.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising one or more output circuits. The output circuits may be configured to configure a bond pad as either an input/output pad, a power pad, or a ground pad in response to a plurality of configuration inputs.
The objects, features and advantages of the present invention include providing a method and/or architecture that may (i) suppress excursions on an internal output power supply node, (ii) optimize performance by implementing power-supply-configurable outputs and I/Os and/or (iii) allow a user to reduce internal noise effects when operating in a high-speed and/or high-current system.


REFERENCES:
patent: 5132555 (1992-07-01), Takahashi
patent: 5574397 (1996-11-01), Tomishima et al.
patent: 5666071 (1997-09-01), Hawkins et al.
patent: 6144542 (2000-11-01), Ker et al.
patent: 6294943 (2001-09-01), Wall et al.
MACH110-12/15/20 High-Density EE CMOS Programmable Logic, May 1995, pp. 1-28.

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