Electrical computers and digital processing systems: processing – Processing control – Logic operation instruction processing
Reexamination Certificate
2000-01-05
2003-04-29
Eng, David Y. (Department: 2155)
Electrical computers and digital processing systems: processing
Processing control
Logic operation instruction processing
Reexamination Certificate
active
06557098
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to computer systems and microprocessors, and more particularly to a multimedia execution unit incorporated within a microprocessor for accommodating high-speed multimedia applications. The invention further relates to extreme value functions and vector processing implemented within microprocessor based systems.
DESCRIPTION OF THE RELATED ART
Microprocessors typically achieve increased performance by partitioning processing tasks into multiple pipeline stages. In this manner, microprocessors may independently be executing various portions of multiple instructions during a single clock cycle. As used herein, the term “clock cycle” refers to an interval of time during which the pipeline stages of a microprocessor perform their intended functions. At the end of the clock cycle, the resulting values are moved to the next pipeline stage.
Microprocessor based computer systems have historically been used primarily for business applications, including word processing and spreadsheets, among others. Increasingly, however, computer systems have evolved toward the use of more real-time applications, including multimedia applications such as video and audio processing, video capture and playback, telephony and speech recognition. Since these multimedia applications are computational intensive, various enhancements have been implemented within microprocessors to improve multimedia performance. For example, some general purpose microprocessors have been enhanced with multimedia execution units configured to execute certain special instructions particularly tailored for multimedia computations. These instructions are often implemented as “vectored” instructions wherein operands for the instructions are partitioned into separate sections or vectors which are independently operated upon in accordance with the instruction definition. For example, a vectored add instruction may include a pair of 32-bit operands, each of which is partitioned into four 8-bit sections. Upon execution of such a vectored add instruction, corresponding 8-bit sections of each operand are independently and concurrently added to obtain four separate and independent addition results. Implementation of such vectored instructions in a computer system furthers the use of parallelism, and typically leads to increased performance for certain applications.
One type of commonly employed function in multimedia applications is a compare function. A compare function is typically implemented though the execution of a compare instruction which compares the value of one operand against another to determine whether the value of the first is greater than, equal to, or less than the other. A compare instruction may be treated as a vectored instruction wherein corresponding sections of associated operands are compared independently of other sections of the operands.
Another set of functions commonly utilized in multimedia processing are the extreme value functions. As used herein, “extreme value functions” are those functions which return either a minimum value selected among a plurality of values, or a maximum value selected among a plurality of values as a result of the function. In typical multimedia systems, a minimum value or a maximum value is obtained through the execution of several sequentially executed instructions. For example, a compare instruction may first be executed to determine the relative magnitudes of a pair of operand values, and subsequently a conditional branch instruction may be executed to determine whether a move operation must be performed to move the extreme value to a destination register or other storage location. These sequences of commands are common in multimedia applications, such as clipping algorithms in graphics rendering systems. Since extreme value functions are implemented through the execution of multiple instructions, however, a relatively large amount of processing time may be consumed by such operations.
It would therefore be desirable to provide a multimedia execution unit in a microprocessor which is capable of obtaining an extreme value through the execution of a single instruction. It would further be desirable to provide a multimedia execution unit with an efficient hardware implementation of the extreme value instructions.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by an execution unit in accordance with the present invention. In one embodiment, an execution unit is provided for executing a first instruction which includes an opcode field, a first operand field, and a second operand field. The execution unit includes a first input register for receiving a first operand specified by a value of the first operand field, and a second input register for receiving a second operand specified by a value of the second operand field. The execution unit further includes a comparator unit which is coupled to receive a value of the opcode field for the first instruction. The comparator unit is also coupled to receive the first and second operand values from the first and second input registers, respectively. The execution further includes a multiplexer which receives a plurality of inputs. These inputs include a first constant value, a second constant value, and the values of the first and second operands. If the decoded opcode value received by the comparator indicates that the first instruction is either a compare or extreme value function, the comparator conveys one or more control signals to the multiplexer for the purpose of selecting an ouput of the multiplexer as the result of the first instruction. If the first instruction is one of a plurality of extreme value instructions, the one or more control signals conveyed by the comparator unit select between the first operand and second operand to determine the result of the first instruction. If the first instruction is one of a plurality of compare instructions, the one or more control signals conveyed by the comparator unit select between the first and second constant value to determine the result of the first instruction. In the case of the compare instructions, the value of the first and second constants may be advantageously chosen in order to form a mask for use by subsequent instructions. In another embodiment, a similar execution unit is provided which handles vector operands.
The extreme value functions are thus implemented in a single instruction. This advantageously results in improved performance for these instruction, which are particularly important in multimedia applications. An efficient hardware implementation is also achieved as the circuitry used for the extreme value operations is also shared by a plurality of compare operations.
Broadly speaking, the present invention contemplates a microprocessor configured to execute a first instruction, wherein an encoded representation of said first instruction includes an opcode field, a first operand field, and a second operand field. The microprocessor comprises an execution unit coupled to receive a decoded value of the opcode field, a first operand specified by a value of the first operand field, and a second operand specified by a value of the second operand field, wherein the execution unit is configured to perform an extreme value operation on the first operand and the second operand in response to receiving the decoded value of the opcode field. The execution unit is further configured to convey an output value of the extreme value operation as a result of the first instruction.
The present invention further contemplates an execution unit in a microprocessor for executing a first instruction, wherein an encoded representation of the first instruction includes an opcode field, a first operand field, and a second operand field. The execution unit comprises a first input register coupled to receive a first operand specified by a value of the first operand field and a second input register coupled to receive a second operand specified by a value of the second operand field. The execution further comprises a
Juffa Norbert
Oberman Stuart
Advanced Micro Devices , Inc.
Eng David Y.
Kivlin B. Noäl
Meyertons Hood Kivlin Kowert & Goetzel P.C.
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