Active solid-state devices (e.g. – transistors – solid-state diode – With means to increase breakdown voltage threshold – Field relief electrode
Reexamination Certificate
2000-02-18
2003-09-02
Eckert, II, George C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
With means to increase breakdown voltage threshold
Field relief electrode
C257S488000, C257S659000
Reexamination Certificate
active
06614088
ABSTRACT:
BACKGROUND OF THE INVENTION
A known method for achieving optimized high breakdown voltages in MOS devices uses lateral drain extensions sometimes called lateral drift regions. Examples of such structures are shown and described in U. S. Pat. Nos. 4,823,173 and 5,264,719. These lateral drain extensions and drift regions may include single dopants of the same type as the source and drain or may include two types of dopants to establish a JFET (junction field effect transistor) drain extension.
Lateral DMOS devices, especially those with drain extensions, are often built with a second level conductor over the lateral extensions or over the entire device. See, for example,
FIG. 1
where the second level of metal M
2
extends over the entire device
10
. The second level metal M
2
performs two functions. It protects the device from diffusion of mobile impurities from the plastic package material and it protects the device from light which could cause photogenerated leakage current. Such lateral DMOS devices are often incorporated into multichip packages where one chip is a light-emitting diode and the second chip has a photodiode coupled to one or more DMOS devices. This type of combination package is used to provide a relay that can be turned on and off without a mechanical switch. The M
2
layer shields the operating DMOS devices from the light emitted by the LED.
However, I have found that while the M
2
layer prevents impurities from entering the substrate, nevertheless, impurities from the plastic packaging material penetrate the M
2
layer and can alter the breakdown characteristics of the underlying transistor. Charges accumulate in the M
2
layer and the accumulated charges adversely affect the voltage at the surface of the transistor. These effects are most noticeable in regions such as region
4
where the first level metal terminates between two contacts that are maintained at high voltage differentials. For example, in a typical DMOS device, the source contact
32
and the drain contact
30
may be at a voltage differential of 100 or more volts. Any accumulated charge on the upper level metal M
2
will affect the electric fields in the region
5
of the substrate that is between the terminations of the two contacts
32
,
30
.
In power DMOS devices it is desirable to have a high, or at least a constant, breakdown voltage. I have found that the breakdown voltage of the device is a maximum when the voltage of the M
2
layer is at a value between the source voltage and the drain voltage. However, the breakdown voltage falls to a lower value when the voltage on M
2
is either the source voltage or the drain voltage.
There are several ways of controlling the voltage on M
2
. It is possible to provide optimum bias on M
2
without any direct electrical connection to it by allowing its voltage to be set by a capacitor divider action. In the capacitor divider configuration, the capacitors are formed by M
2
and the source contact
32
and M
2
and the drain contact
30
. However, that method of biasing with a floating M
1
by capacitor coupling is unreliable. During high temperature burn in when large drain-to-source bias voltages are applied, the breakdown voltage degrades. I believe this degradation is caused by charge migration of charges through the plastic package material and into the layer M
2
. I believe these charge the M
2
to a voltage near the drain or source voltage. Accordingly, there is a need for a more reliable and effective structure and method for improving breakdown voltage control and high voltage semiconductor devices.
SUMMARY
The problem is solved and the breakdown voltage is improved by forming a high value resistive voltage divider between the source and drain and by connecting the M
2
layer to the divider node. Such a divider applies the desired voltage between source and drain voltages to M
2
. The divider drains off any charge that drifts to M
2
through the package during operation. In other words, if the voltage across the source and drain differs by 100 volts, then the larger voltage divider is set to put the node between the resistive elements at 50 volts. Any charge that accumulates in M
2
is drained off through the resistive voltage divider. The very low drainage currents have no adverse affect on the device.
The divider elements need not be linear so long as they create a suitable M
2
voltage for any drain-to-source voltage. The divider should conduct low current at all drain voltages because its current adds to the off leakage of the MOS device to which it is connected. The two resistive elements can be identical to set the divider node at a voltage midway between the source and drain voltage. However, any resistive values that move the node from either the source or drain voltage improves performance.
The preferred embodiment of the invention is made in the same layer of polysilicon that is used for making the MOS gates. The polysilicon is suitably doped using one or more of the drain extension doping steps. This method allows resistors to be made simultaneously with existing process steps, thereby simplifying the method of manufacture. The only changes necessary in manufacture are a few extra masking changes to form the polysilicon resistors.
There are many other methods that could be used to make resistive elements and all such methods are deemed within the scope of the invention. For example, the resistors can be made from trench polysilicon resistors as taught in my U. S. Pat. No. 5,466,963, the entire disclosure of which is herein incorporated by reference. That patent discloses processes which employ trench isolation. The resistive divider could also be made from this series of reverse biased diodes that are formed in polysilicon. That technique exploits the leaky nature of such diodes to provide the required low current to M
2
. And still another embodiment of the invention a slightly conductive dielectric between M
1
an M
2
layers could be used as the divider since the slightly conductive dielectric would create resistors between the layers M
1
and M
2
with layer M
2
connected to a first resistor in contact with the M
1
source contact
32
and a second resistor in contact with the M
1
drain contact
30
.
This resistive divider biasing circuit can be applied to all MOS devices as well as to non-MOS devices which use lateral extensions to maximize their breakdown voltage. Such devices include high voltage diodes, bipolar transistors, SCRs and IGBTs.
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patent: 5264719 (1993-11-01), Beasom
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International Search Report-PCT/US01/03701.
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