Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-03-08
2003-12-09
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C438S309000
Reexamination Certificate
active
06662344
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method for fabricating the same, and more particular to technology that is effective when applied to bipolar transistor-based semiconductor devices of the insulating element isolation type.
One known type of semiconductor device includes a base substrate and an element-forming semiconductor layer with an insulating layer disposed between them. Devices of this type include SOI (Silicon On Insulator) devices and devices in which the element-forming semiconductor layer is divided into a plurality of semiconductor islands by isolation trenches or trenches into which an insulating material is filled. An SOI semiconductor device has quite less parasitic capacitance than a pn-junction element isolation semiconductor device and has smaller leakage current, thereby making it possible to increase the processing speed and reduce power consumption, so this technology has been applied to BiCMOS and C-Bipolar semiconductor devices with digital circuits, analog circuits or a mixture of both types, configured with bipolar and CMOS (Complementary-MOS) transistors and complementary bipolar transistors, respectively. The SOI semiconductor device also requires various types of bipolar transistors with different current capacities for various types of application circuits including logic circuits, driver circuits, and output circuits.
The bipolar transistor-based SOI semiconductor device technology that has been studied by the inventors of the present invention provides a plurality of types of large-current bipolar transistors in different geometrical sizes, and arranges and connects these large-current bipolar transistors depending on current capacities (allowable currents) required, thereby configuring an entire semiconductor device.
SUMMARY OF THE INVENTION
The inventors of the present invention found that the technology described above, however, has the following problems.
The necessity of preparing various types of bipolar transistors increases the number of device parameters that must be defined, and accordingly makes the tuning of analog circuit characteristics very complicated, resulting in an increase in the number of fabrication processes and complexity of tasks for design of semiconductor devices.
More specifically, if various types of bipolar transistors having different allowable currents obtained by changing the geometrical dimensions, are formed, since the geometrical dimensions including the size of semiconductor islands surrounded by isolation-element isolation grooves, areas of emitter and collector junctions, and electrode connection area for emitter, base, and collector regions, or the impurity concentration distributions vary depending on the transistors, the device parameters differs depending on the transistors, which makes the design complicated. In addition, it is possible that electrical characteristics of transistor devices, such as amplification gains, base resistances, and noise factors, may depend on their geometrical dimensions.
The inventor of the present invention examined known examples of bipolar transistor-based semiconductor device technology. One of the examples, which has been disclosed in JP-A-102916/1999, configures the first stage of a multistage amplifier by parallel-connecting bipolar transistors of a structure with a plurality of single emitters that are separated from each other by field insulating films formed by the local oxidation of silicon (LOCOS) method and pn junctions.
It is accordingly an object of the present invention to provide technology that can reduce the number of design processes for semiconductor devices.
Another object of the present invention is to provide semiconductor devices with improved electrical characteristics of large-current transistors.
These and other objects and features of the present invention will become clear in the following detailed description, when read with reference to the attached drawings.
The main features of the invention disclosed herein can be summarized as follows.
The present invention configures a large current capacity bipolar transistor by parallel-connecting a plurality of unit bipolar transistors that are completely electrically isolated from each other in a semiconductor layer on an SOI substrate.
The present invention configures a transistor that yields a desired current capacity by connecting a plurality of unit bipolar transistors that are substantially the same in geometrical dimensions in parallel.
The present invention arranges a plurality of unit bipolar transistors in a matrix to form one bipolar transistor with a large current capacity.
The present invention configures a parallel-connection wiring in multi-layer wiring. For example, emitter, base, and collector contact regions are connected in parallel, by the first and second layer wiring.
The present invention configures a plurality of types of bipolar transistors that differ in the number of unit transistors parallel-connected therein, in the SOI substrate (chip) included in a semiconductor device, thereby enabling configuration of a plurality of bipolar transistors that differ in allowable current from each other. One practical configuration contains a logic circuit portion configured by using unit transistors with comparatively small allowable current (current consumption) and an analog output circuit portion configured by using a bipolar transistor made of many transistors connected in parallel, having a comparatively large allowable current. Although the geometrical dimensions of the unit transistors are not expressly limited, they can be determined with reference to the dimensions of transistors that are utilized most frequently to configure the semiconductor device, such as transistors in the logic circuitry. The dimensions of the unit transistors may be determined also with reference to dimensions that are limited by their minimum workable dimensions.
In addition, the present invention can determine the allowable current uniquely by changing the number of parallel-connected unit transistors of identical size. Therefore, the design of the transistors becomes simply a matter of specifying this number. Furthermore, a comparatively large-current transistor can be configured by wiring unit transistors of identical size together in parallel to obtain the necessary size, whereby degradation of characteristics of base resistance and other circuit parameters can be avoided. For an SOI semiconductor device in which transfer rates of heat radiated from the large-current transistors are particularly lowered, heat can be dissipated through wiring for the parallel connection.
The other features of the present invention will be understood from the following descriptions of the embodiments.
REFERENCES:
patent: 5663662 (1997-09-01), Kurosawa
patent: 6442735 (2002-08-01), Joshi et al.
Iwasaki Takayuki
Kamada Chiyoshi
Tamaki Yoichi
Tsuji Kousuke
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