Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-01-24
2003-06-17
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S629000, C438S687000
Reexamination Certificate
active
06579785
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-016189, filed Jan. 25, 2000; and No. 2000-089289, filed Mar. 28, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to the technology for multi-layer wiring, and in particular, to a semiconductor device having a wiring which is entirely covered by a barrier layer, and to a method of manufacturing such a semiconductor device.
Since Cu in a Cu-wiring would act as a life time killer, it is indispensable for the purpose of inhibiting Cu from diffusing into an interlayer insulating film to provide a barrier layer on the surface of the Cu-wiring which is contact with the interlayer insulating film. Additionally, it is also required to form another barrier layer on the upper surface of the Cu-wiring for the purpose of preventing the upper surface of the Cu-wiring from being oxidized during the manufacturing process of semiconductor device.
As for the upper barrier layer to be formed on the upper surface of the Cu-wiring, silicon nitride film has been conventionally employed. The employment of this silicon nitride film, however, is accompanied with a problem that the capacitance between intralevel wirings is caused to increase due to the fact that the dielectric constant of silicon nitride is relatively high.
With a view to overcome the aforementioned problem, there has been proposed a method wherein a barrier layer which is the same as or equivalent to that employed for the sidewalls and bottom surfaces of the Cu-wiring is employed for covering the upper surface of the Cu-wiring, thereby completely enclosing the Cu-wiring with the barrier layer. A method has been proposed to obtain this structure wherein a Cu-damascene wiring is formed at first, and then, so-called recess etching is performed so as to enable the upper surface of the Cu-wiring to be recessed from the surface of the surrounding interlayer insulating film, after which a barrier layer is deposited all over the wafer and then, the barrier layer is removed by means of the CMP (Chemical Mechanical Polishing) method except the portions thereof which are deposited on the Cu-wiring.
It is desirable in this case to minimize the depth of the recess in order to minimize the capacitance between intralevel wirings. However, if the depth of the recess is minimized, it may become difficult to leave a barrier layer having a sufficient thickness in the recess throughout the entire pattern thereof on the wafer due to the non-uniformity of the polishing velocity in-plane of the CMP (Chemical Mechanical Polishing) or due to the phenomenon of dishing.
Even though the capacitance between intralevel wirings may be increased somewhat, it is possible, by increasing the depth of the recess, to overcome the aforementioned problem accompanied with the CMP. However, since the magnitude of step between the surface of barrier layer and the surface of the insulating film after the formation of the barrier layer becomes too large, it invites another problem that it becomes difficult to ensure a sufficient coverage of films to be deposited thereon in the following steps such as the deposition of an oxide film.
A popular method is to employ a PVD or a CVD method for forming a barrier layer after so-called “recess etching step”. However, it is necessary, for that purpose, to deposit the barrier layer on the bottom of the recessed portion, which is constituted by the surface of wiring. Therefore, if the step coverage characteristic to be obtained by the PVD or CVD is insufficient, it would become impossible to enable the barrier layer to sufficiently exhibit its function.
Further, the process of forming a barrier layer on the upper surface of wiring is generally consisted of the steps of; performing the CMP for forming a wiring, performing the recess etching of the upper portion of wiring; cleaning the resultant surface (if required); forming a barrier layer; removing a redundant portion of the barrier layer by means of the CMP; and performing the CMP again (if required).
In this process, all of the steps excluding the step of forming a barrier layer are generally performed by a wet treatment. Therefore, if the step of forming a barrier layer can be performed by a wet treatment, it may become possible that a sequence of the entire steps can be continuously performed inside a wet system device. Meantime, a wet plating method is known to be useful in realizing an excellent step coverage characteristic, and therefore, the employment of this wet plating method would be convenient since it makes it possible to secure a continuous processing of all of the aforementioned steps in a wet system.
Under the circumstances, an electroless plating method is now tried as a wet type method for forming a barrier layer. Since it is possible, according to this electroless plating method, to selectively form a metal film in conformity with partitioned wiring, it seems to be apparently a promising method. As a matter of fact however, the method is actually accompanied with much restrictions. Namely, due to the specific principle of the electroless plating method, the kinds of metal that can be formed into a film on the surface of the metal wiring is extremely limited. Actually, in the case where a barrier layer is to be formed on the upper surface of a copper wiring that has been formed by means of the damascene method, there is no metal film that can be suitably formed on the copper wiring.
On the other hand, since the electro-plating method is designed to be performed in such a way that metal ions are electro-deposited on the surface of electroconductive film, the electro-plating method can be hardly influenced by the kinds of plating material. However, it is required in the case of electro-plating method to apply a sufficient electric potential to the wiring for performing the plating. However, since the wiring is partitioned into a plurality of sections at the moment of depositing a metal film on the surface of the wiring according to the ordinary manufacturing step, it is impossible to transmit a plating current to the entire sections of wiring.
Additionally, the following problems have been found when an acid is employed in the step of recess etching of Cu-wiring. Namely, the etching is accelerated especially at the interface between the barrier layer and the Cu-wiring, so that the magnitude of recess becomes more prominent at the sidewall portion of the Cu-wiring than at the central portion of the Cu-wiring. Further, the magnitude of recess is dependent not only on the particular region within the wafer but also on the configuration of the pattern of Cu-wiring. As a result, it has been impossible to sufficiently secure the coverage (covering characteristic) of the barrier layer at the sidewall portion of Cu-wiring in a subsequent step of forming a barrier layer, thereby raising various problems that the Cu-wiring may be oxidized during the subsequent steps, and that the diffusion of Cu is caused to occur, thus deteriorating the yield. There is also a problem that it is difficult to obtain a desired characteristic of semiconductor device due to a difference in resistance of wiring among the surface regions of wafer or among the patterns of wiring.
BRIEF SUMMARY OF THE INVENTION
Therefore, an object of this invention is to provide a method of manufacturing a semiconductor device, which is capable of minimizing the magnitude of step between the upper surface of wiring and the upper surface of insulating layer even if the magnitude of recess is increased for securing a sufficient residual film thickness of a barrier layer covering the upper surface of the wiring, thereby making it possible to overcome various problems such as an insufficient coverage of an insulating film to be formed in a subsequent step due to a large step between the upper surface of wiring and the upper surface of insulating layer, and also making it possible to inhibit the
Hirabayashi Hideaki
Kaneko Hisashi
Matsuda Tetsuo
Toyoda Hiroshi
Cuneo Kamand
Geyer Scott B.
Kabushiki Kaisha Toshiba
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