Electrical computers and digital processing systems: processing – Processing control
Patent
1996-12-17
1999-08-17
Maung, Zarni
Electrical computers and digital processing systems: processing
Processing control
712225, 712215, 712 23, G06F 1128, G06F 1134
Patent
active
059387602
ABSTRACT:
A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.
REFERENCES:
patent: 5632023 (1997-05-01), White et al.
patent: 5691920 (1997-11-01), Levine et al.
patent: 5734856 (1998-03-01), Wang
patent: 5752062 (1998-05-01), Gover et al.
Performance Monitor, PowerPC 604 RISC Microprocessor User's Manual, Chapter 9, pp. 9-1 through 9-11, IBM 1994.
Levine Frank Eliot
Moore Roy Stuart
Roth Charles Philip
Welbon Edward Hugh
Barot Bharat
International Business Machines - Corporation
Kordzik Kelly K.
Maung Zarni
LandOfFree
System and method for performance monitoring of instructions in does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for performance monitoring of instructions in , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for performance monitoring of instructions in will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-311061