Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-06-11
2003-07-01
Nelms, David (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06588005
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor integrated circuit device and a manufacturing method thereof, and particularly relates to a technique effectively applied to a semiconductor integrated circuit device having a wiring pattern formed by a lithography technique adopting a phase shift and to a manufacturing technique therefor.
BACKGROUND ART
A lithography technique adopting a Levenson type phase shift capable of improving resolution by ensuring a fixed focal depth has been studied as one of methods of forming a fine wiring pattern.
There have been proposed several methods of arranging phase shifters for a phase shift mask. For example, Japanese Patent Laid-open No. 7-234500 by Ohi et al. discloses a method of executing compaction, in which patterns have the same phase, other patterns between and adjacent to the patterns are given as opposite a phase as possible, and the condition is added that the shortest distance S
1
between the other patterns having the opposite phase is below the shortest distance S
2
between the patterns having the same phase (S
1
<S
2
).
Further, Japanese Patent Laid-open No. 9-152709 by Sawada discloses a method of selecting sequentially phase-undefined patterns, determining phases of the selected patterns in accordance with adjacent pattern phase information thereof so as to be different from phases which most patterns adjacent to the selected patterns have, and updating contents of data of the determined phases.
In addition, Japanese Patent Laid-open No. 6-85202 by Tanaka et al. discloses a method of designing placement of phase shifters in a direction of each shorter dimension of patterns so that relationships between phases of light beams emitted from both openings and other openings adjacent thereto are always opposite to each other.
Also, Japanese Patent Laid-open No. 5-304211 by Itoh discloses a method of connecting a set of boundary wiring formed by making amounts of phase shift changed gradually, to one set of wiring formed by a phase shift method and the other set of wiring formed by no phase shift method.
Further, Japanese Patent Laid-open No. 7-13326 by Ohi et al. discloses a method of obtaining an adjacency relationship depending on whether the shortest length between figures corresponding to transparent regions in mask layout data is below a certain threshold value, giving a weight to each of portions becoming closed loops constituting odd nodes in accordance with the adjacency relationship, and thereby determining the phase of light with respect to the respective transparent regions.
Moreover, Japanese Patent Laid-open No. 6-35171 by Takekuma discloses a method of separating pattern data into an actual pattern data layer and a phase shift pattern data layer, and then verifying a mask pattern.
DISCLOSURE OF THE INVENTION
Although it is possible to narrow wiring placement intervals by using the above-mentioned Levenson type phase shift, there occurs the problem that parasitic capacity (coupling capacity) between sets of wiring increases and thereby delay time of each set of wiring increases.
Further, when a phase shift mask is manufactured, because a designer must redesign each shape, dimension, and position of phase shifters and must manually rearrange the phase shifters relative to contradictory portions which cannot invert a phase, a step of designing a mask pattern requires longer time.
An object of the present invention is to provide a technique capable of preventing the parasitic capacity between the sets of wiring from increasing, and capable of narrowing the wiring placement intervals.
Another object of the present invention is to provide a technique capable of efficiently carrying out phase shift mask design operation.
These and other objects of the present invention as well as novel features of the present invention will be readily apparent from the description of the present specification and accompanying drawings.
Among the inventions disclosed in the present application, typical inventions will be outlined briefly as follows.
(1) According to the semiconductor integrated circuit device of the present invention, a set of wiring transferred by Levenson type phase shift exposure and included in an automatic routing region is constituted by a first wiring group having a first width and a second wiring group having a second width; and said first width is relatively larger than said second width.
(2) According to the semiconductor integrated circuit device of the present invention based on above-mentioned (1), an interval between a set of first wiring and a set of second wiring is narrower than a minimum wiring interval provided without using Levenson type phase shift, the set of second of wiring being put between the adjacent sets of first wiring.
(3) According to the semiconductor integrated circuit device of the present invention based on above-mentioned (2), said first wiring is longer than said second wiring.
(4) According to the semiconductor integrated circuit device of the present invention based on above-mentioned (3), plural sets of second wiring are placed between a pair of sets of first wiring adjacent to each other.
(5) According to the semiconductor integrated circuit device of the present invention, a set of signal wiring placed in a wiring region formed in a semiconductor chip is divided into a set of long wiring and a set of short wiring by comparison with a reference value; and said set of long wiring is arranged in parallel to said set of short wiring and in proximity to at least one side of said set of short wiring.
(6) According to the semiconductor integrated circuit device of the present invention based on above-mentioned (5), an interval between said set of long wiring and said set of short wiring provided in parallel and in proximity thereto is narrow relatively narrower than an interval between sets of long wiring provided in parallel to each other.
(7) According to the semiconductor integrated circuit device of the present invention based on above-mentioned (5), a width of said set of short wiring is 0.3 to 1.0 times as large as a width of said set of long wiring.
(8) According to the semiconductor integrated circuit device of the present invention based on above-mentioned (6), a width of said set of short wiring is 0.3 to 1.0 times as large as a width of said set of long wiring.
(9) According to the semiconductor integrated circuit device of the present invention based on above-mentioned (5), wiring layer constituting a set of signal wiring extending in lateral direction differs from a wiring layer constituting a set of signal wiring extending in longitudinal direction; and the wiring layer extending in the lateral direction and the wiring layer extending in the longitudinal direction, which constitute one-net, are connected to each other through a contact hole provided in an interlayer insulating film between said wiring layer extending in the lateral direction and said wiring layer extending in the longitudinal direction.
(10) According to the semiconductor integrated circuit device of the present invention based on above-mentioned (5), said reference value is K times as high as an average value of spreads of a net in the wiring region, M times as large as a width of an interior of the wiring region, N% of the spread of the net on a shorter side in a wiring length distribution, one of an allowable length of the set of short wiring in view of resistance characteristics determined by a current density of the set of wiring and an allowable length of the set of long wiring in view of capacitive characteristics, and a combination thereof.
(11) The manufacturing method of the semiconductor integrated circuit device of the present invention, comprises the steps of: having a first wiring group with a first width and a second wiring group with a second width; and transferring a wiring pattern in an automatic routing region by Levenson type phase shift exposure, the wiring pattern in which said first width is relatively larger than said second width.
(12) According to the manufactu
Kobayashi Kazuhiko
Miyazaki Kou
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Le Thao
Nelms David
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