Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-02-19
2003-08-19
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06608355
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to semiconductor integrated circuits that can achieve desired operations by writing data within it after the completion of the fabrication process. This invention also relates to methods of fabricating the integrated circuits and writing data into the integrated circuits.
2. Description of Related Art
Recently, programmable semiconductor integrated circuits have become widely used. In these semiconductor integrated circuits, desired circuit operations can be achieved by writing required programming data in the finished products, i.e., products that have already been completed by the fabrication process. These programmable semiconductor integrated circuits are particularly useful for diversified products with limited production amounts.
There are various programming technologies for use in these semiconductor integrated circuits. One example of such programming technology uses so-called anti-fuses. An anti-fuse is a device that changes from a non-conductive state to a conductive state in response to certain catalysts such as an application of a voltage higher than the normal operating voltage.
For example, a MOS transistor can be used as an anti-fuse such as shown in U.S. Pat. Nos. 5,019,878 and 5,673,994, hereby incorporated by reference in their entireties. For example, U.S. Pat. No. 5,019,878 discloses a method to make an N-channel MOS (hereinafter referred to as an “NMOS”) transistor conductive by applying a programming voltage from the drain region to the source region of the NMOS transistor to form a melt filament across the channel region.
A diode including a PN junction can also be used as an anti-fuse such as shown in U.S. Pat. No. 4,646,427 hereby incorporated by reference in its entirety. This prior art reference discloses a method of making a diode conductive by applying a high reverse voltage to form a bridging metal link that shorts out the diode.
When these technologies are applied to actual use, a high voltage of 10 V or greater is necessary to make the anti-fuse conductive.
In order to write data to an NMOS transistor or a diode functioning as an anti-fuse, a writing circuit for supplying the high voltage (writing voltage) is necessary. Generally, the writing circuit is constructed with MOS transistors that are fabricated along with the NMOS transistor or the diode functioning as the anti-fuse on the same semiconductor substrate. When writing programming data, the writing voltage is also supplied to the writing circuit. As a result, the MOS transistor forming the writing circuit may be damaged.
U.S. Pat. No. 5,068,696 described above, proposes a method for lowering the required writing voltage by applying an appropriate voltage to the gate of the NMOS transistor simultaneously with the programming voltage to the drain. However, this method requires another power supply for applying the gate voltage in addition to the power supply for supplying the writing voltage, and hence the configuration of the writing circuit becomes more complex.
The technology described in the U.S. Pat. No. 4,646,427 utilizes a diode formed in a polysilicon film, which is known to be effective in lowering the required writing voltage. With this method alone, however, it is difficult to satisfactorily lower the required writing voltage.
SUMMARY OF THE INVENTION
Accordingly, the present invention described in the preferred embodiments provides a semiconductor integrated circuit having an anti-fuse, a method of fabricating the semiconductor integrated circuit, and a method of writing data in the semiconductor integrated circuit, in which the programming data can be written by a simple writing circuit without damaging other elements in the semiconductor integrated circuit.
It is an object of the present invention to provide semiconductor integrated circuit that is able to solve the problems of the above-described conventional technology.
In order to achieved this object, one aspect of the present invention provides a semiconductor integrated circuit including a semiconductor substrate having a surface, a first and second MOS transistors formed on the surface of the semiconductor substrate and a writing circuit integrated on the surface of the semiconductor substrate. Each of the first and the second MOS transistors has a first conductivity type source and drain region and a second conductivity type channel region between the source and drain regions. The first MOS transistor has a first drain-source breakdown voltage and the second MOS transistor has a second drain source breakdown voltage lower than the first drain source breakdown voltage. The writing circuit supplies a writing voltage between the drain and the source regions of the second MOS transistor to make the second MOS transistor conductive.
In an exemplary embodiment, at least a portion of the channel region adjacent to the drain region of the second MOS transistor includes a channel impurity of the second conductivity type with a concentration higher than that at a corresponding portion of the first MOS transistor. Preferably, the channel region of the second MOS transistor extends between two ends along an edge of the drain region and at least one of the portions adjacent to the ends of the channel region includes a channel impurity of the second conductivity type with a first concentration higher than that at a first corresponding portion of the first MOS transistor. Further preferably, a center portion between the ends of the channel region of the second MOS transistor includes the channel impurity with a second concentration higher than that at a second corresponding portion of the first MOS transistor.
According to another aspect of the invention, a method of fabricating a semiconductor integrated circuit including a first and second MOS transistor and a writing circuit that supplies a writing voltage to the second MOS transistor is provided. The fabrication method includes forming the first and second MOS transistors on a surface of a semiconductor substrate. Each of the first and second MOS transistors has a first conductivity type source and drain region and a second conductivity type channel region between the source and drain regions. The first MOS transistor has a first drain source breakdown voltage and the second MOS transistor has a second drain source breakdown voltage lower than the first drain-source breakdown voltage. The second drain source breakdown voltage being sufficiently low so that the second MOS transistor becomes conductive when the writing circuit supplies the writing voltage between the drain and the source regions of the second MOS transistor.
In an exemplary embodiment, the method also includes forming the first and the second MOS transistors such that at least a portion of the channel region adjacent to the drain region of the second MOS transistor includes a channel impurity of the second conductivity type with a concentration higher than that at a corresponding portion of the first MOS transistor. Preferably, the first and the second MOS transistors are formed by selectively implanting the channel impurity in at least a portion of a second surface area of the semiconductor substrate without implanting the channel impurity in a corresponding portion of a first surface area. The second surface area surrounds a second surface region of the semiconductor substrate that will become a second active region including the source, drain, and channel regions of the second MOS transistor. The first surface area surrounds a first surface region of the semiconductor substrate that will become a first active region including the source, drain, and channel regions of the first MOS transistor.
According to another aspect of the invention, a method of writing data in a semiconductor integrated circuit is provided. The method includes providing a first and second MOS transistor on a surface of a semiconductor substrate. Each of the first and second MOS transistors has a first conductivity type source and drain region and a second conductivit
Aoike Junji
Ariyoshi Ryuji
Fukushima Takahito
Kuno Isamu
Kawasaki Microelectronics, Ltd.
Oliff & Berridg,e PLC
Wilson Allan R.
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