Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-07-09
2003-04-15
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S288000, C257S368000, C257S758000
Reexamination Certificate
active
06548847
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor technology and, more particularly, to a technology which is effected when applied to a semiconductor integrated circuit device having a DRAM (i.e., Dynamic Random Access Memory) and to a technology for forming the former.
A memory cell of the DRAM for latching an information of 1 [bit] is constructed of a series circuit between a memory cell selecting MISFET and a information storing capacity element. The memory cell selecting MISFET of the aforementioned memory cell is formed over the principal surface of the active regions of a semiconductor substrate (or well regions). The active regions of the semiconductor substrate are formed within the region which are surrounded by an element separating insulating film (i.e., a field insulating film) formed in the inactive regions of the aforementioned semiconductor substrate and channel stopper regions. The aforementioned memory cell selecting MISFET has its gate electrodes connected with word lines extending in a row direction. One of the semiconductor regions of the memory cell selecting MISFET are connected with complementary data lines. The other semiconductor regions are connected with one of the electrode of the aforementioned information storing capacity element. This information storing capacity element has its other electrode supplied with a predetermined potential.
The DRAM of this kind has a tendency of being integrated to have a larger capacity and having its memory cells small-sized. In case the size of the memory cells is reduced, the size of the information storing capacity element is also reduced so that the amount of charge storage or information is dropped. This reduction in the charge storage will drop the a &agr;-ray soft error withstand voltage. Therefore, it is an important technical target of the DRAM having a capacity as large as 1 [Mbit] or more to improve the a &agr;-ray soft error withstand voltage.
On the basis of this technical target, there is a tendency that-the stacked structure (i.e,. STC structure) is adopted in the information storing capacity element of the memory cell of the DRAM. The information storing capacity element of this stacked structure is constructed by laminating a lower electrode layer, a dielectric film and an upper electrode layer sequentially. The lower electrode layer is partially connected with other semiconductor region of the memory cell selecting MISFET and has its other portion extended to over the gate electrodes. The upper electrode layer is formed over the aforementioned lower electrode layer through a dielectric film. This upper electrode layer is integrated with the upper electrode layer of the information storing capacity element of the stacked structure of another adjoining memory cell so that it may be used as a common plate electrode.
Incidentally, the DRAM acting as the information storing capacity element of the stacked structure and constructing the memory cell is disclosed in U.S. application Ser. No. 07/246,514 filed on Sep. 19, 1988, for example.
SUMMARY OF THE INVENTION
We have found the following problems during the development of a DRAM having a capacity as high as 16 [Mbits].
In the DRAM, the separations of the memory cells are accomplished at present at an element separating insulating film and channel stopper regions. The element separating insulating film is formed by oxidizing the principal surface of the inactive regions of the semiconductor substrate by using a non-oxidizable mask (of a silicon nitride film) formed over the principal surface of the active regions of the semiconductor substrate. On the other hand, the channel stopper regions are formed of an impurity such as B, which is introduced into the principal surface portions of the active regions (i.e., only the memory cell array) and the inactive regions of the semiconductor substrate. This impurity is introduced, after the element separating insulating film has been formed, by the ion implantation method using such a high energy as to transmit the element separating insulating film. More specifically, the impurity introduced into the principal surface portions of the inactive regions of the semiconductor substrate below the element separating insulating film is formed as the aforementioned channel stopper regions. Since the impurity thus introduced into the principal surface portions of the active regions of the semiconductor substrate is introduced into deeper regions than the impurity introduced into the principal surface portions of the inactive regions, it will not adversely affect the memory cells. The process of forming the channel stopper regions using the ion implantation method using that high energy is featured in that it can reduce the narrow channel effect of the memory cell selecting MISFET. Specifically, the aforementioned forming process can form the channel stopper regions in self-alignment with the element separating insulating film so that it can reduce the amount of diffusion of the impurity for forming the channel stopper regions to the active regions.
However, the DRAM being developed by us is intended to have a capacity as large as 16 [Mbits] so that it cannot-retain the memory cell area and the memory cell separating area sufficiently. In other words, the aforementioned element separating insulating film has a large amount of oxidization (i.e., bird's beak) in a transverse direction so that the area of the element separating insulating film is augmented more than necessary. This augmentation of the area of the element separating insulating film in turn shrinks the memory area more than necessary. In case, therefore, the aforementioned element separating insulating film is thinned to reduce the amount of transverse oxidization, the shallow regions of the principal surface portions of the active regions of the semiconductor substrate are doped with an impurity for forming the channel stopper regions. The impurity thus introduced into the principal surface portions of the active regions of the semiconductor substrate enhances the impurity concentration of the surface so that it fluctuates the threshold voltage of the memory cell selecting MISFET of the memory cell. As a result, the memory cell area can neither be retained, not can be shrunk the separating area of the memory cells, thus raising a problem that the DRAM cannot be highly integrated.
The present invention has the following objects:
(1) to provide a technology capable improving the degree of integration in a semiconductor integrated circuit device having a storing function;
(2) to provide a technology capable of improving the electric reliability in the aforementioned semiconductor integrated circuit device;
(3) to provide a technology capable of improving the soft error withstand voltage in the aforementioned semiconductor integrated circuit device;
(4) to provide a technology capable of reducing the number of fabrication steps in the aforementioned semiconductor integrated circuit device;
(5) to provide a technology capable of improving the treating accuracy for the fabrications in the aforementioned semiconductor integrated circuit device;
(6) to provide a technology capable of improving the drivability of the semiconductor elements in the aforementioned semiconductor integrated circuit device;
(7) to provide a technology capable of improving the fabrication yield in the aforementioned semiconductor integrated circuit device;
(8) to provide a technology capable of increasing the operating speed in the aforementioned semiconductor integrated circuit device;
(9) to provide a technology capable of preventing the defects such as the disconnections of wiring lines in the aforementioned semiconductor integrated circuit device;
(10) to provide a technology capable of improving a moisture resistance in the aforementioned semiconductor integrated circuit device;
(11) to provide a technology capable of simplifying the steps of forming redundancy fuse elements in the aforementioned semiconductor inte
Akimori Hiroyuki
Aoki Hideo
Asano Isamu
Enami Hiromichi
Funatsu Keisuke
Antonelli Terry Stout & Kraus LLP
Fenty Jesse A.
Hitachi , Ltd.
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