Semiconductor device with fuse to be blown with energy beam...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S601000, C438S618000, C438S642000, C438S648000, C438S687000, C438S613000, C438S128000, C438S129000, C438S132000, C438S215000, C438S281000, C438S333000, C257S355000, C257S532000, C257S529000, C257S209000, C257S750000, C257S762000, C029S623000, C327S525000

Reexamination Certificate

active

06656826

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. P2000-293941 filed on Sep. 27, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. In particular, the present invention relates to a semiconductor device with copper wiring and a fuse that forms part of a redundancy circuit and a method of manufacturing such a semiconductor device. The present invention also relates to a semiconductor device with protrusion electrodes (bumps) for flip-chip packaging and a method of manufacturing such a semiconductor device.
2. Description of the Related Art
Semiconductor integrated circuit devices are improving in functions and capacities through finely thinned elements and multileveled wiring. The fine elements and multileveled wiring tend to cause defects during semiconductor chip manufacturing, to decrease the yield of semiconductor chips. A typical technique, of repairing such defects during semiconductor device manufacturing and improving the yield of semiconductor products, is a redundancy circuit technique. This technique prepares spare elements in a semiconductor chip in advance, and if defective elements are found in the chip, replaces the defective elements with the spare elements, thereby repairing the chip. For example, a column or row of memory cells, containing a defective memory cell in a semiconductor memory, is replaced with spare memory cells. Replacing defective elements with spare elements is carried out by blowing a fuse. The fuse forms a part of the redundancy circuit containing the spare elements. Blowing the fuse is carried out by laser or electricity. The fuse is generally formed from polycrystalline silicon or metal.
In a semiconductor chip packaging field, wireless bonding, that may replace wire bonding, is studied and practiced. An example of the wireless bonding is flip-chip packaging. The flip-chip packaging forms bumps serving as electrodes on the surface of a semiconductor chip, reverses the chip, positions the bumps on electrodes of a circuit board, and connects them together by facedown bonding. In this way, the semiconductor chip is installed on the circuit board. The flip-chip packaging is ideal to reduce the size of a semiconductor package and increase the density of elements in the semiconductor package.
To reduce resistance and improve reliability, recent semiconductor devices frequently employ copper (Cu) wiring instead of aluminum (Al) wiring. To increase scale and density, recent semiconductor devices frequently employ multileveled wiring. For example, high-speed SRAMs employ four-level wiring, and logic LSIs with memories employ wiring of five or more levels. Generally, upper wiring levels are made to be thicker than lower wiring levels, to stabilize a power source voltage.
SUMMARY OF THE INVENTION
An aspect of the present invention provides a semiconductor device having copper wiring levels formed on a semiconductor substrate on which semiconductor elements are formed, an uppermost wiring level formed on the copper wiring levels and including a refractory metal film connected to a top one of the copper wiring levels, a fuse formed from a part of the uppermost wiring level, to be blown with an energy beam, and a surface protective film formed on the uppermost wiring level.


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patent: 5-114655 (1993-05-01), None
patent: 11-340265 (1999-12-01), None
patent: 3177968 (2001-04-01), None

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