Nonvolatile semiconductor memory device and manufacturing...

Details Nonvolatile semiconductor memory device and manufacturing... Nonvolatile semiconductor memory device and manufacturing...

2002-05-07

2003-12-30

Ho, Hoai (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S302000, C257S315000

Reexamination Certificate

active

06670666

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and, more specifically, to a structure of a source diffusion layer region of a non-volatile semiconductor memory device and to a manufacturing method thereof.
2. Description of the Background Art
As a method of isolating each cell region of a non-volatile semiconductor memory device represented by a conventional flash memory, element isolating structure utilizing formation of an isolation film through LOCOS (local oxidation of silicon) process has been dominant. The LOCOS isolation, however, has a limit in miniaturization of the semiconductor devices, and hence STI (Shallow Trench Isolation) comes to be widely used recently. In STI, a trench is formed at a main surface of a semiconductor substrate and filled with a burying oxide film, so as to establish element isolation.
A non-volatile semiconductor memory device having a common trench isolation suffers from a problem that a source diffusion layer region comes to have high resistance when self align source etching is performed utilizing anisotropic dry etching. In a non-volatile semiconductor memory device using LOCOS isolation, an end portion of an isolation film has moderate inclination. Therefore, a source diffusion layer interconnection of low resistance is formed between respective sources at the time of ion implantation, and therefore, such a problem does not arise. In the trench isolation described above, a sidewall of the trench formed at the main surface of the semiconductor substrate has a steep inclination of approximately 90°. Therefore, it has been difficult to form a source diffusion layer interconnection of low resistance on the sidewall during ion implantation.
In the following, a structure of a non-volatile semiconductor memory device employing the conventional trench isolation as well as the problem mentioned above will be described in greater detail.
FIG. 6
is a top view representing a structure of a conventional non-volatile semiconductor memory device, and
FIGS. 7
to
10
are cross sections showing various portions of the non-volatile semiconductor memory device.
In the non-volatile semiconductor memory device, when the main surface of the semiconductor is viewed from above, cells forming a memory portion are arranged in a matrix. Along a bit line (BL) direction of the cells arranged in a matrix, a plurality of trench isolation regions
17
are formed as stripes parallel to each other at the main surface of a semiconductor substrate
1
. Along a word line (WL) direction, gate regions
15
are formed at the main surface of the semiconductor substrate
1
. The gate region
15
includes a floating gate
5
and a control gate
6
. A source diffusion layer region
2
and a drain region
4
are formed sandwiching the gate region
15
. Drain region
4
is electrically isolated by the above described trench isolation region
17
. A drain electrode
12
for taking out electrical charges is formed in each drain region
4
. Source diffusion layer region
2
is constituted by individual source regions
2
a
arranged along the word line direction electrically connected with each other by source diffusion layer interconnections
2
b
. Source diffusion layer interconnection
2
b
is formed by removing an isolation film positioned between individual source regions
2
a
by etching so as to expose a trench surface of semiconductor substrate
1
, and by performing ion implantation to the thus exposed trench surface of semiconductor substrate
1
. Thus, the source regions
2
a
aligned in the word line direction are electrically coupled, so that all have the same potential. The aforementioned floating gate
5
is arranged independently for each cell, between source region
2
and drain region
4
.
Cross sectional structures of respective regions will be described in detail in the following. First,
FIG. 7
is a cross section taken along the line VII—VII of FIG.
6
. Referring to the figure, the main surface of the semiconductor in the source diffusion layer region
2
has recesses and protrusions. This shape results from the above described process in which a trench isolation film
17
provided at the main surface of semiconductor substrate
1
is removed to expose the trench portion. Source diffusion layer region
2
continuously extends immediately below the surface of the recesses and protrusions. Further, an interlayer insulating film
11
is formed to cover the main surface of semiconductor substrate
1
.
FIG. 8
is a cross section taken along the line VIII—VIII of FIG.
6
. Referring to this figure, drain regions
4
of the cells are isolated by trench isolation
17
from each other, and on each drain region
4
, a drain electrode
12
is formed. Different from the above described source region
2
a
, drain regions
4
aligned in the word line direction are electrically independent from each other, and therefore, electric charges are taken out from each drain region
4
through drain electrode
12
.
FIG. 9
is a cross section taken along the line IX—IX of FIG.
6
. Referring to the figure, in the cross section of semiconductor substrate
1
along the direction of extension of a gate region
15
, a channel
8
is formed at the main surface of the semiconductor substrate
1
sandwiched between trench isolation regions
17
, and a floating gate
5
is positioned with a thin tunnel oxide film
18
interposed, on the channel
8
. An upper surface of floating gate
5
is covered by a control gate
6
with a thin ONO (oxide nitride oxide) film
20
interposed, thus providing a capacitance. Further, at an upper portion of control gate
6
, a gate electrode
7
is formed for taking out electrical charges from the control gate.
FIG. 10
is a cross sectional view taken along the line X—X of FIG.
6
. Referring to the figure, in the cross section along the bit line direction of the non-volatile semiconductor memory device, source regions
2
a
and drain regions
4
are arranged alternately at the main surface of semiconductor substrate
1
, and between each of these regions, a channel
8
is positioned. Immediately above the channel
8
, a floating gate
5
is positioned with a thin tunnel oxide film
18
interposed, and on an upper surface of floating gate
5
, control gate
6
and gate electrode
7
are positioned, with the aforementioned ONO film
20
interposed. The non-volatile semiconductor memory device having such a structure is thus formed.
The method of forming the source diffusion layer region in the non-volatile semiconductor memory device having the above described structure is as follows.
FIGS. 11A and 11B
are cross sections representing the method of forming the non-volatile semiconductor memory device having the above described structure. First, a trench is formed at the main surface of semiconductor substrate
1
, the trench is filled with an isolation film to form a trench isolation region
17
, and the isolation film of that portion of the trench isolation region
17
which overlaps the source diffusion layer region
2
is removed by self align source etching. Consequently, the main surface of semiconductor substrate
1
at a portion that will be source diffusion layer region
2
comes to have such a cross sectional structure as shown in
FIG. 11A
, which includes recesses and protrusions.
Thereafter, an n type impurity such as arsenic is ion-implanted to the portion that will be source diffusion layer region
2
, from a direction approximately at a right angle with the main surface of semiconductor substrate
1
(from the direction of the arrow D in the figure). As the upper surface of the protrusions are positioned approximately at a right angle with respect to the direction of ion implantation, a deep source region
2
a
is formed immediately therebelow. Further, as the bottom surface of the recesses is positioned approximately at a right angle with respect to the direction of ion implantation, a deep source diffusion layer interconnection
2
b
1
is formed immediately ther

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