Method for configuring an intelligent low power serial bus

Details Method for configuring an intelligent low power serial bus Method for configuring an intelligent low power serial bus

1995-08-18

1999-08-17

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Input/output data processing

Peripheral configuration

710 8, 710260, G06F 1300, G06F 1314

Patent

active

059387424

ABSTRACT:
A low power, single master, variable clock rate, daisy-chainable, serial bus connects a bus dispatch (master) to a chain of one or more daisy-chained peripheral devices (slaves). The bus has a bidirectional serial data line, a bidirectional clock line, unidirectional interrupt line, power and ground lines. A method for configuring the bus includes detecting connection and disconnection of a peripheral device to the bus. In the method, a last peripheral device on the bus is assigned the second status and all other peripheral devices on the bus are assigned the first status. Each peripheral device assigned the first status is configured to pass therethrough an interrupt signal on the bus. The last peripheral device is configured to invert an interrupt signal on the bus from a peripheral device that is newly attached to the bus. A peripheral device newly connected to the bus generates an interrupt signal that is inverted by the last peripheral device and transmitted over the bus to a host computer for the bus. Also, an interrupt signal is driven on the bus by one peripheral device on the bus upon disconnection of another peripheral device on the bus where the another peripheral device is downstream on the bus from the one peripheral device.

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patent: 5636342 (1997-06-01), Jeffries

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