Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2000-06-29
2003-06-10
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S158000, C711S117000, C711S100000, C709S225000, C370S503000, C370S395610
Reexamination Certificate
active
06578109
ABSTRACT:
BACKGROUND SECTION
1. Field of the Invention
This invention relates generally to techniques for optimizing processor operations, and relates more particularly to a system and method for effectively implementing isochronous processor cache.
2. Description of the Background Art
Implementing effective methods for optimizing processor operations is a significant consideration for designers and manufacturers of contemporary electronic devices. A processor in an electronic network may advantageously communicate with other electronic devices in the network to share data to thereby substantially increase the capabilities and versatility of individual devices in the electronic network. For example, an electronic network may be implemented in a home environment to enable flexible and beneficial sharing of data and device resources between various consumer electronic devices, such as personal computers, digital video disc (DVD) devices, digital set-top boxes for digital broadcasting, enhanced television sets, and audio reproduction systems.
Effectively managing processor operations in a network of electronic devices may create substantial challenges for designers of electronic networks. For example, enhanced demands for increased device functionality and performance during data transfer operations may require more system processing power and require additional hardware resources across the network. An increase in processing or hardware requirements may also result in a corresponding detrimental economic impact due to increased production costs and operational inefficiencies.
Furthermore, enhanced device capability to perform various advanced processor operations may provide additional benefits to a system user, but may also place increased demands on the control and management of the various devices in the electronic network. For example, an enhanced electronic network that effectively accesses, processes, and displays digital television programming may benefit from efficient processing techniques because of the large amount and complexity of the digital data involved.
One type of processing that may occur in an electronic network is an isochronous process. Isochronous processes include the guaranteed handling of data that arrives in a time-based stream at regular intervals called cycles. Isochronous processes are typically used for time-sensitive applications. For example, video or audio data being transmitted across a network typically needs to arrive at a display device in an uninterrupted flow with appropriate timing.
Due to growing demands on system resources and substantially increasing data magnitudes, it is apparent that developing new and effective methods for optimizing processor operations is a matter of significant concern for the related electronic technologies. Therefore, for all the foregoing reasons, implementing effective methods for optimizing and facilitating processor operations remains a significant consideration for designers, manufacturers, and users of contemporary electronic devices.
SUMMARY
In accordance with the present invention, a system and method are disclosed for effectively implementing isochronous processor cache. In one embodiment, a computer device includes a central processing unit (CPU), a memory device, and a system bus that is isolated from an I/O bus by an I/O bus bridge. In practice, various types of information and data (including isochronous data) are preferably transferred bidirectionally by the computer device between the memory device and the I/O bus via the system bus and the I/O bus bridge.
In addition, the computer device preferably includes a cache memory that communicates bidirectionally with the memory device and the I/O bus bridge via the system bus. The cache memory also communicates bidirectionally with the CPU via a CPU bus. In other embodiments, the cache memory may alternately be implemented using various other appropriate configurations and architectures.
In certain embodiments, the cache memory may include an asynchronous cache for temporarily storing asynchronous data from various sources. In accordance with the present invention, the cache memory also preferably includes an isochronous cache that may advantageously be locked from access by other types of data transfers. The isochronous cache may also be flexibly reconfigured with regards to various selectable attributes such as data size and the number of different isochronous processes that are supported.
Isochronous data typically is time-sensitive data that is assigned a high transfer and processing priority to guarantee that the isochronous data deterministically arrives at pre-determined timing intervals and is processed accordingly. Ensuring the timely and guaranteed arrival of isochronous data at the CPU becomes a matter of some significance when implementing the computer device. The computer device may therefore flexibly reserve a reconfigurable portion of the cache memory as the isochronous cache to ensure deterministic performance of isochronous processes, in accordance with the present invention. The present invention thus provides an improved system and method for effectively implementing isochronous processor cache to optimize processor operations.
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Fairman Bruce A.
Smyers Scott D.
Stone Glen D.
Kim Matthew
Koerner Gregory L.
Li Zhou H.
Simon & Koerner LLP
Sony Corporation
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