Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

2002-06-26

2003-06-24

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S315000

Reexamination Certificate

active

06583467

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and particularly, to a technique which can be advantageously applied to improvements of reliability of a non-volatile semiconductor memory device.
BACKGROUND OF THE INVENTION
Known as an electrically rewritable non-volatile semiconductor memory device is a so-called AND-type Flash memory described in the Japanese Patent Application Laid-Open Publication No. 07-273231. This publication describes the following manufacturing method as a technique for improving the integration of transistors called as memory cells in the chips.
That is, a three-layer film comprised of a gate oxide film, a first polycrystal silicon layer, and a silicon nitride film is coated on a semiconductor substrate made of monocrystal silicon. These layered films are patterned into stripe shapes. Next, n-type impurities are implanted into such a portion of the semiconductor substrate that is not covered by the patterned layer film, thereby to form column lines of an n-type impurity semiconductor region on the surface of the semiconductor substrate. Next, a CVD (Chemical Vapor Deposition) oxide film is coated thereon, and thereafter, a silicon oxide film formed by the CVD method is etched thereby to form a side wall spacer on the side wall portions of the first polycrystal silicon layer and the silicon nitride film. Next, using the first polycrystal silicon layer and the side wall spacer as a mask, grooves are formed on the semiconductor substrate by anisotropic dry etching. In this manner, the n-type impurity semiconductor region is separated, and column lines and source lines are each formed. Next, a silicon oxide film is formed on the surface of the grooves. Thereafter, the second polycrystal silicon layer is coated (deposited) on the entire surface of the semiconductor substrate, and the second polycrystal silicon layer is etched back by isotropic dry etching until the silicon nitride film is exposed. Next, the surface of the second polycrystal silicon layer which has been etched back is oxidized, thereby to form an element separation region made of polycrystal silicon covered with a silicon oxide film. Subsequently, the silicon nitride film is removed, and a third polycrystal silicon layer is coated. Patterning is carried out so as to protect the first polycrystal silicon layer. Floating gates parallel to the column lines are thus formed. Next, an interlayer insulating film and a fourth polycrystal silicon layer are coated, and patterning is carried out, thereby to form row lines which are made of the forth polycrystal silicon layer and are vertical to the column lines. In this manner, the first and third polycrystal silicon layers are separated from each other, and floating gates are formed.
In the AND-type flash memory formed in this kind of method, the semiconductor device is constructed to have a non-volatile memory function by storing electrons in the floating gates. In particular, n-type impurity semiconductor regions formed in both sides of the first polycrystal silicon layer serve as source or drain regions. In this method, processing on the first polycrystal silicon layer and formation of the element separation region are achieved by a mask pattern of one single layer. Therefore, no matching margin is necessary between the gates and the element separation region, so the cell area is reduced to be small.
As a method for much higher integration of an AND-type flash memory, for example, the PCT International Publication No. WO98/44567 describes a technique in which a shallow-groove-type element separation region is formed on the main surface of a semiconductor substrate and a memory cell is formed in an active region surrounded by the element separation region. In the technique according to this publication, the element separation region is formed like a stripe, so that the active region is formed also like a stripe. The lower electrode of a floating gate is formed also like a stripe, layered on a center portion of the active region. With this lower electrode used as a mask, an ion implantation method is applied so that source lines and data lines are formed by self-alignment in the active region. Thereafter, an insulating film is filled between the lower electrodes. Upper electrodes of floating gates are formed as an upper layer thereof. In this manner, the area of the upper electrode is enlarged so that coupling with a control gate (word line) is enhanced and down-sizing is realized simultaneously.
SUMMARY OF THE INVENTION
However, the present inventors have found the following problems in the technique for forming a stripe-like element separation region as described above.
That is, many leakages have been found to occur between the sources and drains of memory elements (i.e., between source lines and data lines) in case where stripe-like element separation regions are formed and an active region is formed to be inserted between element separation regions. Therefore, this is a large obstacle which hinders securing of the reliability and the yield of the semiconductor integrated circuit device.
According to the experiments and discussions made by the present inventors, it has been found that a defective leakage is one of factors that cause an element junction leakage. FIG.
54
(
a
) is a TEM photograph when an active region (channel portion) of a portion which causes a defect is observed. FIG.
54
(
b
) is a schematic view in which FIG.
54
(
a
) is traced. An active region ACL is formed between element separation regions SGI, and a floating gate electrode FG is formed on the active region ACL with a tunnel oxide film FNO inserted therebetween. On the floating gate electrode FG, a control gate electrode CG is formed with an inter-layer insulating film INS inserted therebetween. The control gate electrode CG is constructed in a two-layer structure comprised of a polycrystal silicon film and a tungsten silicide film. As shown in FIG.
54
(
b
), a crystal defect D is formed on the active region ACL. It is considered that a leakage current is caused due to this kind of crystal defect.
Even if existence of a crystal defect does not directly involve an element defect, it is considered that it may become a factor which deteriorates the reliability. FIG.
55
(
a
) is a circuit diagram which explains a read sequence, and FIG.
55
(
b
) is a graph showing discharge-time-dependence of the number of defective sectors that cause a read error. As shown in FIG.
55
(
a
), a read sequence from memory cells turns on a STD and turns off a STS, thereby to charge (precharge) electric charges from a global data line to a local data line. Next, the STS is turned on and the local source line is connected to a common source line, thereby to discharge the remaining electric charges from the local source line. Thereafter, the SDT is turned off to start sensing. In the sensing, a necessary voltage is applied to word lines (control gates), and each memory cell transistor is turned on or off in correspondence with the charge amount stored in its floating gate. If it is turned on, the electric potential of the local data line is lowered. This potential can be detected by a sense amplifier, so information in the memory cell can be extracted. At this time, if the electric potential of the local source line is not at a sufficiently low value, the following situation appears. Remaining electric charges exist in the local source line and therefore, the electric potential is not lowered, although the memory cell transistor is turned on and the potential of the local data line is lowered. That is, a read error is caused. Therefore, it is necessary to spend a sufficient time discharging electric charges from the local source line prior to the sensing. However, as shown in FIG.
55
(
b
), there has been an experimental result showing that the number of defective sectors increases if the discharge time is elongated. Occurrence of defective sectors in accordance with increase of the discharge

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